A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.

Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

Multiple data paths may be available to a data management system for transferring data between a primary storage device and a secondary storage device. The data management system may be able to gain operational advantages by performing load balancing across the multiple data paths. The system may use application layer characteristics of the data for transferring from a primary storage to a backup storage during data backup operation, and correspondingly from a secondary or backup storage system to a primary storage system during restoration.

A system and method for improving deduplication techniques in a data storage system. In one embodiment, a data storage system is configured to divide first data into a first plurality of segments, to generate a first plurality of fingerprints that are each to be associated with a segment, to identify second data that is to be updated by the first data and a second plurality of fingerprints associated with the second data, to load the second data and the second plurality of fingerprints from persistent storage of the data storage system into working memory, to determine, in the working memory, that a first segment of the first plurality of segments updates the second data by comparing a first fingerprint associated with the first segment to the second plurality of fingerprints, and to overwrite a second segment of the second data with the first segment in response to the determination.

An embedded processing unit (eCPU) processes an input/output (I/O) request from a host using a virtual storage controller. The eCPU associates a virtual network interface with a host. The virtual storage controller uses a first transport protocol. The eCPU receives an I/O request directed at a storage device from the virtual storage controller. The eCPU determines a second transport protocol used by the storage device, and converts the I/O request from a format according to the first transport protocol to a format according to the second transport protocol. The eCPU transmits the I/O request to the storage device using the second transport protocol.

An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins.

A memory system may include: a memory device comprising a plurality of pages, which include a plurality of memory cells coupled to a plurality of word lines, and in which data is stored, and a plurality of memory blocks in which the pages are included; and a controller configured to divide the memory blocks into a first group and a second group, perform a command operation corresponding to a command received from a host, and respectively store segments of user data and meta data for the command operation in memory blocks included in the first group or memory blocks included in the second group, in accordance with type information of the user data Included in the command.

Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.

A system and method employing a distributed hardware architecture, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations are disclosed. A compute node may be implemented independent of a host compute system to manage and to execute data processing operations. Additionally, an unique algorithm architecture and processing system and method are also disclosed. Different types of nodes may be implemented, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations.

A flash-based storage warehouse system includes flash memory devices and reader/writer devices that are moveable to different locations in a structure. Each of the flash memory devices are at one of the different locations in the structure. Each of the reader/writer devices includes a locomotion apparatus configured to move the corresponding one of the reader/writer devices to a different location in the structure and a processor coupled to a memory and the locomotion apparatus that is configured to execute machine executable code to: engage the locomotion apparatus to adjustably position one of reader/writer devices to one of the locations in the structure in response to a received operation; couple power via the corresponding one of the reader/writer devices to one of the flash memory devices at the one of the locations in the structure; and execute the operation on the flash memory device at the location in the structure.