Patent classifications
G06F3/0626
Maintaining metadata associated with a replicated dataset
Symmetric storage using a cloud-based storage system, including: receiving, at a cloud-based storage system among storage systems synchronously replicating a dataset, an I/O operation directed to the dataset; determining, in dependence upon the I/O operation, a metadata update describing a mapping of segments of content to an address within a storage object, wherein the storage object includes the dataset; and synchronizing metadata on another storage system of the storage systems by sending the metadata update from the cloud-based storage system to the other storage system to update a metadata representation on the second storage system in accordance with the metadata update.
Supplemental AI processing in memory
Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator.
ADAPTIVE COMPRESSION FOR ACCELERATOR DEVICES
An accelerator device may access an input data chunk to be compressed by the accelerator device. The accelerator device may access an entropy value for the input data chunk. The accelerator device may compress the input data chunk or return an indication that the input data chunk will not be compressed based on the entropy value and an entropy threshold.
DEDUPLICATING DATA INTEGRITY CHECKS ACROSS SYSTEMS
A computer-implemented method, according to one embodiment, includes: receiving, at a clustered filesystem from a formatted filesystem, a request to perform a data integrity check for a portion of data. A determination is made as to whether the request includes a filesystem type of the portion of data, and in response to determining that the request includes a filesystem type of the portion of data, another determination is made as to whether the clustered filesystem supports the data integrity check for the filesystem type. In response to determining the clustered filesystem supports the data integrity check, another determination is made as to whether the portion of data is currently available. Furthermore, the computer-implemented method includes causing the data integrity check to be performed in response to determining that the portion of data is currently available. Results of performing the data integrity check are also sent to the formatted filesystem.
On-demand activation of memory path during sleep or active modes
A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.
System and method for caching data in persistent memory of a non-volatile memory express storage array enclosure
A method, computer program product, and computing system for receiving, via a storage processor of a storage system, a write request for writing a data portion to a storage array enclosure of non-volatile memory express (NVMe) drives communicatively coupled to the storage processor, where the write request may be received from a host. The data portion may be written to a persistent memory write cache within the storage array enclosure.
DATA PROCESSING SYSTEM AND DATA COMPRESSION METHOD
Provided is a data processing system which includes a processor and a storage device, and inputs/outputs data using a learned compander that compresses and expands data, wherein the data processing system comprises an estimation unit which uses learning data and estimates a region of interest to a data model, and a learning unit which causes the compander to learn according to an evaluation function in which each region was weighted based on the region of interest, and a result of the compander compressing and expanding the learning data.
Enhanced filesystem support for zone namespace memory
A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.
Address/command chip controlled data chip address sequencing for a distributed memory buffer system
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
Controller, memory controller, storage device, and method of operating the controller
A controller for use in a memory device includes an error information generator configured to receive error information about an error occurring while a command is being processed at a protocol layer, generate command error information corresponding to the command based on the received error information, and store the generated command error information in a first storage area, and an error information manager configured to store the command error information, stored in the first storage area, in a second storage area in response to an external request.