G06F3/0638

STORAGE SYSTEM AND METHOD FOR ACCESSING SAME
20230049799 · 2023-02-16 ·

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Distributed processing method and apparatus based on consistency protocol and storage medium

A distributed processing method based on a consistency protocol is provided. The method includes: transmitting a decree prepare request including a first decree number, the decree prepare request requesting other nodes to promise to no longer accept a fast write operation initiated by a leader node whose leader number is less than the first decree number, the first decree number representing a leader number of a current node, and the leader number representing a number of a decree at which the current node that becomes a leader node is located; and in response to receiving decree promises from at least a preset quantity of nodes among the other nodes, enabling the fast write operation from a subsequent decree number of a second decree number determined based on the decree promises, each of the decree promises including the first decree number.

Storage device storing data on key-value basis and operating method thereof

A storage device includes a controller configured to: receive, from a host, a plurality of key-value pairs, separate a key from each of the plurality of key-value pairs and a value therefrom, and generate a first key stream by merging a plurality of keys separated from the plurality of key-value pairs, and non-volatile memory configured to store the first key stream. The first key stream is stored, separately from the value separated from each of the plurality of key-value pairs, in the non-volatile memory.

Data storage method, device, related equipment and cloud system for hybrid cloud

Embodiments of this application provide a hybrid-cloud data storage method and apparatus, a related device, and a cloud system. The data storage method includes: obtaining, by a gateway of a private cloud, to-be-stored data; determining partial data to be encrypted in the to-be-stored data, to obtain first target data; obtaining a first ciphertext obtained after the first target data is encrypted, the first target data being encrypted according to a first key provided by an encryption chip connected to the gateway; generating second target data including the first ciphertext according to the first ciphertext; generating a data slice corresponding to the second target data according to the second target data; and transmitting the data slice corresponding to the second target data to a public cloud for storage.

Data Compression in Integrated Device Network
20230037575 · 2023-02-09 ·

An integrated circuit is provided that includes compression or decompression circuitry along a datapath. An integrated circuit system may include first memory to store data, data utilization circuitry to operate on the data, and a configurable data distribution path to transfer data between the first memory and the data utilization circuitry. Compression or decompression circuitry may be disposed along the data distribution path between the first memory and the data utilization circuitry to enable the first memory to store the data in compressed form and to enable the data utilization circuitry to operate on the data in uncompressed form. The compression or decompression circuitry may use lossless sparse encoding, lossless multi-precision encoding, lossless prefix lookup table-based encoding, Huffman encoding, selective compression, or lossy compression.

Enhanced network attached storage (NAS) services interfacing to cloud storage

An illustrative storage management appliance is interposed between client computing devices and one or more cloud storage resources. The appliance uses cloud storage resources in conjunction with a network attached storage device configured within the appliance to provide to the client computing devices seemingly unlimited network attached storage on respective network shares. The storage management appliance monitors data objects on the network shares and when a data object meets one or more criteria for archiving, the storage management appliance archives the data object to a cloud storage resource and replaces it with a stub and preview image on the network share. When access to the stub and/or preview image is detected, the storage management appliance restores the data object from the cloud storage resource. The criteria for archiving flexibly allow individual data objects to be archived to cloud storage without archiving frequently-accessed “neighboring” data objects on the same network share.

Protection of objects in an object store from deletion or overwriting

An illustrative method includes an object retention management system establishing a retention policy for a bucket of an object-based storage system, detecting an operation that causes an object to be stored within the bucket, and applying, based on the detecting of the operation, the retention policy to the object, the retention policy preventing the object from being deleted or overwritten for a predefined time duration.

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEVEL MEMORY DEVICE TO CACHE DATA PRESENT IN A SECOND LEVEL MEMORY DEVICE

Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2.sup.n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

MEMORY ACCESS MODULE FOR PERFORMING MEMORY ACCESS MANAGEMENT
20180012651 · 2018-01-11 ·

A memory access module for performing memory access management of a storage device includes a plurality of storage cells. Each storage cell has a number of possible bit(s) directly corresponding to possible states of the storage cell. The memory access module further includes: sensing means for performing a plurality of sensing operations, wherein a first sensing operation corresponds to a first sensing voltage, and each subsequent sensing operation corresponds to a sensing voltage determined according to a result of the previous sensing operation; generating means for using the plurality of sensing operations to generate a first digital value and a second digital value of a storage cell; processing means for using the first and the second digital value to obtain soft information of a same bit stored in the storage cell; and decoding means for using the soft information to perform soft decoding.

Storage system with multiplane segments and cooperative flash management

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.