G06F3/0638

Data processing system performing neural network operations and operating method thereof
11669249 · 2023-06-06 · ·

A data processing system, which performs a neural network operation in response to a request from a host, comprising: a controller configured to receive control information and the input data from the host and to generate the output data by performing an operation on the input data and the weight, the control information including a scheme for storing a parameter including input data, output data, and a weight and a scheme for reusing the weight; and a memory device configured to store the weight according to control of the controller as the weight is transmitted from the host, wherein the controller includes an address converter configured to map a physical address provided from the host to a memory address based on the parameter storing scheme and the weight reusing scheme so that a bandwidth of a reading operation of the weight is maximized.

Memory system and operating method for testing target firmware by processing a plurality of test commands
11500563 · 2022-11-15 · ·

Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may, when setting a firmware as a target firmware, generate a plurality of test commands to test the target firmware, test the target firmware by processing the plurality of test commands, and randomly generate logical block address (LBA) values corresponding to each of the plurality of test commands based on a seed value corresponding to each of the plurality of test commands.

MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION
20220357893 · 2022-11-10 ·

An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

Systems and Methods for Correcting Data Errors in Memory

Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Memory preserving parse tree based compression with entropy coding

A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

MEDIA TYPE SELECTION FOR IMAGE DATA

Systems, apparatuses, and methods related to media type selection for image data are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and can write data to the memory media types. Image data inputs can be written (e.g., stored) in a particular type of memory media characteristics. For instance, selection of memory media can be based on one or more attributes of the image data. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, image data from a first image sensor of a plurality of image sensors, identifying one or more attributes of the image data, and writing, based at least in part on the one or more attributes of the image data, the image data to a first memory media type of the plurality of memory media types.

ARCHITECTURE FOR MANAGING I/O AND STORAGE FOR A VIRTUALIZATION ENVIRONMENT
20220350627 · 2022-11-03 · ·

Disclosed is an improved approach to implement I/O and storage device management in a virtualization environment. According to some approaches, a Service VM is employed to control and manage any type of storage device, including directly attached storage in addition to networked and cloud storage. The Service VM implements the Storage Controller logic in the user space, and can be migrated as needed from one node to another. IP-based requests are used to send I/O request to the Service VMs. The Service VM can directly implement storage and I/O optimizations within the direct data access path, without the need for add-on products.

Data storage system with uneven drive wear reduction

A data storage system includes multiple data storage devices. A subset of the data storage devices are selected to implement log storages for the data storage system, wherein incoming read and write requests are serviced at the data storage devices implementing the log storages. Data written to a volume stored in the data storage system is initially written to the log storage and subsequently flushed to additional data storage implemented using remaining ones of the data storage devices of the data storage system. A controller monitors wear levels of the data storage devices and initiates a reorganization of which data storage devices implement the log storages and which data storage devices implement the additional storage such that discrepancies in wear between the data storage devices is reduced.

Placement of data objects in storage for improved retrieval

Systems and methods are provided for utilizing rules for placement of objects in storage in a manner that improves retrieval times relative to a default ordering utilized by an object storage system. For example, a request to store an object in a persistent storage of a data storage system may be received, metadata associated with the request may then be parsed to identify a signal for placement of the object within the persistent storage, and a rule may be identified for placement of objects associated with that signal, such as by indicating a desired grouping or ordering of objects associated with the signal. A particular storage location for the object may then be determined within the persistent storage based at least in part on the signal, the rule, and previously determined storage locations of one or more other data objects associated with the signal.

DYNAMIC MEMORY ADDRESS WRITE POLICY TRANSLATION BASED ON PERFORMANCE NEEDS
20220350539 · 2022-11-03 ·

Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between the first addressing scheme and the second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.