This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

A method for dynamically storing keys and values includes receiving a request for storing one or more keys in a key value Solid State drive (KV-SSD). The method further includes performing a storage operation for storing each key of the one or more keys in a node of a data structure of the KV-SSD. The storage operation includes allocating a first region in the node for storing the key, such that a size of the first region is equal to a size of the key. The storage operation further includes allocating a second region in the node for storing key metadata associated with the key, such that the second region is of a predetermined size. The storage operation further includes storing the key in the first region and the key metadata in the second region of the node.

A processor is to execute a first instruction to perform a simulated return in a program from a callee function to a caller function based on a first input stack pointer encoded with a first security context of a first callee stack frame. To perform the simulated return is to include generating a first simulated stack pointer to the caller stack frame. The processor is further to, in response to identifying an exception handler in the first caller function, execute a second instruction to perform a simulated call based on a second input stack pointer encoded with a second security context of the caller stack frame. To perform the simulated call is to include generating a second simulated stack pointer to a new stack frame containing an encrypted instruction pointer associated with the exception handler. The second simulated stack pointer is to be encoded with a new security context.

Systems, devices and methods for adaptive compression of stored information includes a memory management computing device programmed to monitor a size of a plurality of data structures stored in a data repository. The computing device compares the size of each of a plurality of data structures to a predetermined threshold. When a size of an uncompressed data structure meets the threshold, the memory management computing device calculates a value of a first compression parameter based on a value of a first parameter and a value of a second parameter of each data element of the uncompressed data structure, calculates a value of a second compression parameter based the value of the first parameter of each data element of the uncompressed data structure, generates a compressed data structure based on the value of the first compression parameter and the second compression parameter; and replaces, in the data repository, the uncompressed data structure with the compressed data structure.

A method and apparatus for controlling access to memory is disclosed. In one implementation, a memory controller may receive a memory access request that may include a virtual memory address, a device identifier (ID) and a protected access indicator. Additionally, the memory controller can receive page table entries including a physical memory address based on the virtual memory address and a security attribute associated with the physical memory address. The memory controller may access a memory based on the physical memory address, the security attribute, the protected access indicator, and the device ID.

Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

An illustrative embodiment disclosed herein is an apparatus including a processor and a memory. In some embodiments, the memory includes programmed instructions that, when executed by the processor, cause the apparatus to store a first object and a second object in a first region based on the first object and the second object having a first policy. In some embodiments, the memory includes programmed instructions that, when executed by the processor, cause the apparatus to store a third object in a second region based on the third object having a second policy. In some embodiments, a virtual disk includes the first region and the second region.

A method begins by a load balancing module of a distributed storage network (DSN) determining availability of a plurality of DSN processing units of a set of DSN processing units based on availability information associated with the plurality of DSN processing units and in response to determined availability, selecting a DSN processing unit form the set to process a data access request. The method continues with the load balancing module receiving an indication that the DSN processing unit is no longer available from the DSN processing unit while the DSN processing unit continues to process previously pending data access requests. The method continues with the load balancing module cancelling selection of the DSN processing unit to process the data access request; and receiving a second indication from the DSN processing unit indication that the DSN processing unit is available.

A storage device may include a non-volatile memory including a plurality of zones, the non-volatile memory configured to sequentially store data in at least one of the plurality of zones, and a processing circuitry configured to, receive a first write command and first data from a host, the first write command including a first logical address, identify a first zone of the plurality of zones based on the first logical address, compress the first data based on compression settings corresponding to the first zone, and write the compressed first data to the first zone.

The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.