G06F3/0638

TECHNOLOGIES FOR SWITCHING NETWORK TRAFFIC IN A DATA CENTER

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

Memory Allocation for Block Rebuilding in a Storage Network

A method begins by identifying a plurality of encoded data slices requiring rebuilding. The method continues by determining an amount of memory required for rebuilding the plurality of encoded data slices and allocating memory in one or more storage units for the rebuilding the plurality of encoded data slices as reserve memory. The method continues by obtaining a plurality of rebuilt encoded data slices associated with the plurality of encoded data slices requiring rebuilding and storing the plurality of rebuilt encoded data slices in the reserve memory.

Memory system and SoC including linear address remapping logic
11573716 · 2023-02-07 · ·

A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller dorms a linear access operation on the first or second memory device in response to receiving the remapped address.

Distributed index for fault tolerant object memory fabric
11573699 · 2023-02-07 · ·

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments can implement an object memory fabric including object memory modules storing memory objects created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects within the object memory module. A hierarchy of object routers communicatively coupling the object memory modules may each include a router object directory that indexes all memory objects and portions contained in object memory modules below the object router in the hierarchy. The hierarchy of object routers may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the router object directories.

METHOD, DEVICE, AND COMPUTER PROGRAM PRODUCT FOR TRANSMITTING DATA FOR OBJECT STORAGE
20230100936 · 2023-03-30 ·

Transmission of data for object storage, such as stream transmission for object storage, is disclosed. For instance, a group of objects acquired from an object layer is stored in a storage space for storing an object stream and serves as a first part of the object stream; and, in response to that an event related to at least one object in the group of objects occurs at a client terminal, the event-related information is stored in the storage space and is used as a second part of the object stream, the event-related information including at least one of the following: an identifier of the at least one object, a type of the event, and metadata of the event.

MEMORY MAPPING OF ACTIVATIONS FOR CONVOLUTIONAL NEURAL NETWORK EXECUTIONS

A memory controller circuit for mapping data of a convolutional neural network to a physical memory is disclosed. The memory controller circuit comprises a receiving unit to receive a selection parameter value, and a mapping unit to map pixel values of one layer of the convolutional neural network to memory words of the physical memory according to one of a plurality of mapping schemas, wherein the mapping is dependent on the value of the received selection parameter value.

DATA STREAMING ACCELERATOR

Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry provides high-performance data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.

Tier-Specific Data Compression
20230032590 · 2023-02-02 ·

A method, apparatus, and computer program product for tier-specific data compression, comprising comparing costs associated with a plurality of storage configurations for storing data based on one or more usage characteristics of data, wherein each storage configuration of the plurality of storage configurations corresponds to a particular storage tier of a plurality of storage tiers and a particular compression algorithm of a plurality of compression algorithms and based on the comparison of the costs, storing the data using a storage configuration of the plurality of storage configurations.

Data processing method for improving access performance of memory device and data storage device utilizing the same
11614885 · 2023-03-28 · ·

A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a predetermined memory block as an active memory block to receive data from a host device and accordingly record a plurality of logical addresses in a first mapping table. In response to a determination of recommending for activating one or more sub-regions of the memory device or delivering one or more Host Performance Booster (HPB) entries is required, the memory controller is further configured to update a second mapping table based on the first mapping table before delivering the HPB entries to the host device. The memory controller is further configured to generate the HPB entries according to the second mapping table after the second mapping table has been updated based on the first mapping table and deliver a packet comprising the HPB entries to the host device.

Managed placement of object components in an object-based datastore
11614864 · 2023-03-28 · ·

A method for storage management of an object among a plurality of storage devices of a datacenter is provided. The method, in response to receiving an input on a selection item presented through a UI, determines that a manual storage management of an object is selected. The method then receives a storage policy for storing the object. Based on the storage policy, the method defines a plurality of components for the object and determines whether a set of one or more storage resources is available for storing the plurality of components. When the method determines that the set is available, for each component, the method presents the set of storage resources, receives a selection of a storage resource in the set to store the component, and updates the set based on the policy and the selection before presenting the updated set to select from for storing a next component.