Patent classifications
G06F3/0646
LOCATION-AWARE BEHAVIOR FOR A DATA STORAGE DEVICE
The present disclosure relates to a location-aware data storage device. The data storage device may record previous locations of the data storage device and may identify a pattern of use based on the previous locations. The data storage device may determine a predicted location based on the pattern of use and may activate a storage medium when the data storage device is within a predetermined proximity to the predicted location.
SINGLE-STAGE ARBITER/SCHEDULER FOR A MEMORY SYSTEM COMPRISING A VOLATILE MEMORY AND A SHARED CACHE
Systems, methods, and computer programs are disclosed for scheduling memory transactions. An embodiment of a method comprises determining future memory state data of a dynamic random access memory (DRAM) for a predetermined number of future clock cycles. The DRAM is electrically coupled to a system on chip (SoC). Based on the future memory state data, one of a plurality of pending memory transactions is selected that speculatively optimizes DRAM efficiency. The selected memory transaction is sent to a shared cache controller. If the selected memory transaction results in a cache miss, the selected memory transaction is sent to a DRAM controller.
Data protection with multiple site replication
Systems and methods for replicating data from a first site to a second site remote from said first site are described. An embodiment includes storing compressed data on a hard disk appliance, reading said data without decompressing said data, sending said data over a wide-area-network (WAN) in a compressed state, and storing said data on a second hard disk appliance remote from said first hard disk appliance in its compressed state without performing an additional compression operation.
Asymmetric memory migration in hybrid main memory
Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
APPARATUS AND METHOD FOR ACCELERATING OPERATIONS IN A PROCESSOR WHICH USES SHARED VIRTUAL MEMORY
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
DEDICATED INTERFACE FOR COUPLING FLASH MEMORY AND DYNAMIC RANDOM ACCESS MEMORY
The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.
Network attached device for accessing removable storage media
Embodiments disclosed herein provide systems, methods, and computer readable media to access data on removable storage media via a network attached access device. In a particular embodiment, a method provides receiving one or more user provided, in the removable storage media access device, receiving data over a packet communication network for storage on a removable storage medium. After receiving the data, the method provides preparing the data for storage on the removable storage medium. After preparing the data, the method provides writing the data to the removable storage medium.
Validating Data Integrity During Replication
Verifying that data has been correctly replicated to a replication target, including: replicating a dataset stored at a first computing system to a second computing system; and determining, based at least on a comparison of a first hash and a second hash, validity of the dataset stored at the second computing system, wherein the first hash is generated by applying a hash function to a copy of the dataset that is stored at the first computing system and the second hash is generated by applying the hash function to a copy of the dataset that is stored at the second computing system.
INCREASING OLTP THROUGHPUT BY IMPROVING THE PERFORMANCE OF LOGGING USING PERSISTENT MEMORY STORAGE
In an embodiment, before modifying a persistent ORL (ORL), a database management system (DBMS) persists redo for a transaction and acknowledges that the transaction is committed. Later, the redo is appended onto the ORL. The DBMS stores first redo for a first transaction into a first PRB and second redo for a second transaction into a second PRB. Later, both redo are appended onto an ORL. The DBMS stores redo of first transactions in volatile SRBs (SLBs) respectively of database sessions. That redo is stored in a volatile shared buffer that is shared by the database sessions. Redo of second transactions is stored in the volatile shared buffer, but not in the SLBs. During re-silvering and recovery, the DBMS retrieves redo from fast persistent storage and then appends the redo onto an ORL in slow persistent storage. After re-silvering, during recovery, the redo from the ORL is applied to a persistent database block.
Logical and physical block addressing for efficiently storing data to improve access speed in a data deduplication system
One method includes assigning a pointer from multiple logical blocks to the same original physical block if the multiple logical blocks include the same data. The method further includes receiving a command to write data to the first logical block and determining if the first logical block is a frequently accessed logical block. If the first logical block is a frequently accessed logical block, ownership of the original physical block is assigned to the first logical block. If ownership is established, the method includes copying any data stored in the original physical block to a new physical block, assigning a pointer from a second logical block to the new physical block, and performing the write command on the original physical block. A system includes a processor for performing the above method. One computer program product includes computer code for performing the method described above.