A storage device programs a requested data unit into a second memory block by programming the requested data unit into the first memory block corresponding to a logical address included in the request and updating a mapping relationship between a physical address indicating a first memory block and the logical address and moving the programmed data unit to the second memory block. A controller records the logical address and the physical address in a meta data unit corresponding to the requested data unit and verifies integrity of the mapping relationship for the moved data unit.

A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

A method includes error encoding data to produce a plurality of data slices. Metadata is determined for a data slice of the plurality of data slices. The metadata is stored in a metadata storage tree. The data slice is stored in a slice storage location indicated by the metadata. Based on determining to access the data slice, the metadata for the data slice is accessed in the metadata storage tree to determine the slice storage location for the data slice, and the data slice is accessed in the slice storage location based on determining the slice storage location for the data slice via accessing the metadata storage tree.

Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a large read operation can include receiving a pre-fetch command, a parameter list and a read command at a storage system. In certain examples, the pre-fetch command can provide an indication of the length of the parameter list, and the parameter list can provide location identifiers of the storage system from which the read command can sense the read data.

Executing a machine learning model in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (GPU) servers, including: receiving, by a graphical processing unit (GPU) server, a dataset transformed by a storage system that is external to the GPU server; and executing, by the GPU server, one or more machine learning algorithms using the transformed dataset as input.

A system and method for efficient execution of I/O operations in a storage environment including receiving, by a storage controller, an incoming I/O operation that can be serviced by a storage device while at least one pending operation is to be processed using the storage device, determining, based on an analysis by the storage controller of an operational state of a storage system that includes the storage device, whether processing the at least one pending operation is more efficient than issuing an alternative operation to the storage device, and issuing, by the storage controller, one or more instructions to the storage device.

Implementing a data movement network includes tiling one or more layers of a machine learning model based, at least in part, on amounts of addressable memory available in different memory levels of a memory architecture of an electronic system. Logical connections specifying compute tiles of the electronic system and logical address spaces corresponding to the compute tiles are generated. Physical connections are generated within the memory architecture by binding ports of direct memory access circuits of the memory architecture to the logical connections. Data transfers for memories between the different memory levels are scheduled based, at least in part, on a loop order of the tiling. Buffers for data of the data transfers are placed within the memories based on the scheduling.

An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.