First and second data are identified, such that the second data is based on a modification operation performed on the first data. First error-checking data comprising a Cyclic Redundancy Check (CRC) value of the first data is identified. Incremental error-checking data is generated based on a difference between the first data and the second data. Updated first error-checking data is generated based on a combination of the first error-checking data and the incremental error-checking data. The updated first error-checking data is compared to second error-checking data generated from a CRC value of the second data to determine whether the second data contains an error.

A semiconductor memory device is provided. The semiconductor memory device includes a memory core including a plurality of memory cells configured to store a plurality of data received from an external processor; and a statistical feature extractor disposed on a data path between the external processor and the memory core, the statistical feature extractor being configured to analyze statistical characteristics of the plurality of data, identify at least one statistical feature value associated with the statistical characteristics, store the at least one statistical feature value and transmit the at least one statistical feature value to the external processor.

Several embodiments of systems incorporating memory components are disclosed herein. In one embodiment, a memory system can include a memory component and a processing device configured to access quality metrics corresponding to memory regions of the memory component. In some embodiments, the processing device can compare the quality metrics to one or more memory management thresholds. In some embodiments, when the quality metrics meet and/or exceed a first threshold, a refresh operation can be scheduled and/or performed on a corresponding memory region. In these and other embodiments, when the quality metrics meet and/or exceed a second threshold, the memory region is retired and removed from an active pool of memory regions.

Methods, systems, and devices for volatile register to detect power loss are described. The memory system may receive a command to enter a first power mode having a lower power consumption than a second power mode. The memory system may store data in a register associated with the memory system before entering the first power mode (e.g., a low-power mode). The memory system may receive a command to exit the first power mode. The memory system may determine whether the data stored in the register includes one or more errors. The memory system may select a reset operation to perform to exit the first power mode based on determining whether the data stored in the register includes one or more errors.

A Solid State Drive (SSD) is disclosed. The SSD may comprise flash storage for data, the flash storage organized into a plurality of blocks. A controller may manage reading data from and writing data to the flash storage. Metadata storage may store device-based log data for errors in the SSD. Identification firmware may identify a block responsive to the device-based log data. In some embodiments of the inventive concept, verification firmware may determine whether the suspect block is predicted to fail responsive to both precise block-based data and the device-based log data.

Disclosed is a memory system including a plurality of memory dies configured to store data in various storage modes; and a controller coupled with the plurality of memory dies via a plurality of channels and configured to perform a correlation operation on multiple read requests among a plurality of read requests received from a host so that the plurality of memory dies output plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way, wherein the controller is configured to determine whether to perform the correlation operation based on the number of read requests, and perform the correlation operation on the multiple read requests which are related to the same storage mode and different channels.

A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.

Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

An SPD-based memory monitoring and service life prediction method and system. Said method includes: acquiring parameter information of each memory bank in a server, and setting a weight for the parameter information; reading configuration information of each memory bank, and calculating occupation ratio information of parameters of each memory bank according to the configuration information and the parameter information; calculating state information of each memory bank according to the weight and the occupation ratio information; determining an influence factor according to the number of CPUs in the server and the number and position of memory banks in each CPU; and calculating a final memory state value according to the influence factor and the state information, and according to the used time and the state information of each memory bank, calculating the remaining service life of each memory bank by means of piecewise fitting using a least square method.

A computer-implemented method, a computer program product, and a computer system for data flow management in a heterogeneous memory device. A media controller redirects traffic from first non-volatile memory (NVM) to second NVM, in response to an instantaneous temperature of the first NVM reaches a first predetermined temperature at which redirecting the traffic is started. The media controller throttles to reduce the traffic to the second NVM, in response to determining that the instantaneous temperature is higher than a second predetermined temperature at which throttling is started. The media controller redirects the traffic back to the first NVM, in response to determining that the instantaneous temperature is not higher than the second predetermined temperature and lower than a third predetermined temperature at which throttling is ended. The first NVM is thermally sensitive, while the second NVM is thermally tolerant.