A method for computational storage may include storing, at a storage device, a first portion of data, wherein the first portion of data may include a first fragment of a record, and a second portion of data may include a second fragment of the record, and appending the second fragment of the record to the first portion of data. The method may further include performing, at the storage device, an operation on the first and second fragments of the record. The method may further include determining that the first portion of data may include a first fragment of a record, and a second portion of data may include a second fragment of the record, wherein appending the second fragment of the record to the first portion of data may include appending, based on the determining, the second fragment of the record to the first portion of data.

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

A memory module is provided. The memory module includes: a control chip, at least one data flash memory chip, at least two memory cells, and at least one non-volatile memory, each of the at least one data flash memory chip is connected to at least one of the at least two memory cells and at least one of the at least one non-volatile memory, the control chip is connected to the at least one data flash memory chip and the at least two memory cells, and the memory is further connected to at least one capacitor; the control chip is configured to send a control command; and each of the at least one data flash memory chip is configured to perform, based on the control command from the control chip, data processing between the memory cell connected thereto and the non-volatile memory connected thereto.

A storage system. In some embodiments, the storage system includes a plurality of object stores, and a plurality of data managers, connected to the object stores. The plurality of data managers may include a plurality of processing circuits. A first processing circuit of the plurality of processing circuits may be configured to process primarily input-output operations, and a second processing circuit of the plurality of processing circuits may be configured to process primarily input-output completions.

A traditional storage platform performs many basic functions, such as storage partitions allocation (i.e., namespace masking) and many advanced functions, such as deduplication or dynamic storage allocation. These functions need to be managed and this results in a multiple management system paradigm, in which a fabric management application manages the fabric connectivity policies (i.e., Zoning), while a storage management application manages the storage namespace mappings and advanced functions. Embodiments herein provide for centralized management for both connectivity and storage namespace mapping, among other advanced features. Namespace zoning information may comprise Namespace ZoneGroups, Namespace Zones, Namespace Zone Members, Namespace ZoneAlias, and Namespace ZoneAlias Members, which expand the NVMe-oF zoning framework from just connectivity control to full Namespaces allocation.

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.

A system including a baseboard management controller (BMC) and a socket is described. The BMC is configured to provide a management interface to a network device. The socket is configured to accept an edge connector of a removable storage card. The BMC is configured to access via the socket at least a portion of the firmware of the BMC stored on the removable storage card.

A system, apparatus and product comprising: a multi-tenant layer that comprises shared resources, wherein the shared resources are accessible to multiple tenants of the storage system, wherein the shared resources comprise shared logic resources and shared data resources; and multiple single-tenant layers, wherein each single-tenant layer is associated with a respective tenant of the multiple tenants, wherein each single-tenant layer comprises a database and business logic of the respective tenant, wherein a multi-tenant encryption scheme is configured to enable secure communications with the multiple tenants without divulging sensitive information to the multi-tenant layer.