Patent classifications
G06F3/0655
SYSTEM AND METHOD FOR PRE-SOFT-DECODING TRACKING FOR NAND FLASH MEMORIES
A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain a first soft read sample by performing a first read operation on a location of the flash memory with a first reference voltage. The circuit may be configured to determine a second reference voltage based on the first soft read sample. The circuit may be configured to obtain a second soft read sample by performing a second read operation on the location of the flash memory with the second reference voltage. The circuit may be configured to generate soft information based on the first and second soft read samples. The circuit may be configured to decode a result of a third read operation on the location of the flash memory based on the soft information.
ADDRESS DECODING CIRCUIT, MEMORY, AND CONTROL METHOD
An address decoding circuit includes a decoding unit corresponding to a bank group and including first NAND gates, an address selection signal outputted by each first NAND gate controls a corresponding bank in the bank group corresponding to the decoding unit. The first NAND gate includes a first input end connected to an address signal of a bank corresponding to the first NAND gate and a second input end connected to an output end of a second NAND gate or a third NAND gate, the second NAND gate includes a first input end connected to an enable signal and a second input end connected to a control signal, and the third NAND gate includes a first input end connected to the enable signal and a second input end connected to an inverted signal of the control signal.
TECHNIQUES FOR DISCOVERING DATA STORE LOCATIONS VIA INITIAL SCANNING
A system and method for discovering data store locations. A method includes reading, for each disk of a plurality of disks deployed in a cloud environment, only a portion of a snapshot of the disk accessed via a cloud provider tool, wherein the portion of the snapshot of each disk accessed via the cloud provider tool includes file system metadata of a file system of the disk, wherein the cloud provider tool is configured to provide direct access to data from each of the plurality of disks; analyzing the portion of the snapshot of each disk of the plurality of disks to determine whether each disk contains a data store; and identifying, based on the analysis, at least one data store in the cloud environment.
MEMORY DEVICE AND OPERATING METHOD THEREOF
A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
Endurance groups ECC allocation
A data storage device includes a memory device having a plurality of endurance groups and a controller coupled to the memory device. The controller includes at least one decoder or at least one decoder group. The controller is configured to allocate a plurality of tokens to each endurance group of the plurality of endurance groups, receive a payment of tokens from an endurance group to access the at least one decoder or the at least one decoder group, and grant access to the at least one decoder or the at least one decoder group to the endurance group based on the payment of tokens. Each decoder or each decoder group is associated with the same or different payment of tokens and each endurance group has a maximum capacity of tokens.
Consistent recovery of a dataset
Servicing I/O operations in a cloud-based storage system, including: receiving, by the cloud-based storage system, a request to write data to the cloud-based storage system; storing, in solid-state storage of the cloud-based storage system, the data; storing, in object storage of the cloud-based storage system, the data; detecting that at least some portion of the solid-state storage of the cloud-based storage system has become unavailable; identifying data that was stored in the portion of the solid-state storage of the cloud-based storage system that has become unavailable; retrieving, from object storage of the cloud-based storage system, the data that was stored in the portion of the solid-state storage of the cloud-based storage system that has become unavailable; and storing, in solid-state storage of the cloud-based storage system, the retrieved data.
Collision reduction through just-in-time resource allocation
Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a main memory has memory cells arranged on dies arranged as die sets accessible using parallel channels. A controller is configured to arbitrate resources required by access commands to transfer data to or from the main memory using the parallel channels, to monitor an occurrence rate of collisions between commands requiring an overlapping set of the resources, and to adjust a ratio among different types of commands executed by the controller responsive to the occurrence rate of the collisions. In further embodiments, the controller may divide a full command into multiple partial commands, each of which are executed as the associated system resources become available. In some cases, the ratio is established between read commands and write commands issued to the main memory.
MEMORY CONTROLLER AND OPERATING METHOD THEREOF
The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation is performed based on detection information that indicates a state of the memory device, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase of a threshold voltage distribution of the monitoring memory cells.
Memory comprising memory controller configured to determine a logical address of a target zone system and method of operating the memory controller
A memory system according to the present technology may include a plurality of memory devices including a plurality of blocks configured of memory cells and a memory controller configured to control the plurality of memory devices corresponding to a plurality of zones by configuring the plurality of zones with the plurality of blocks included in each of the plurality of memory devices, wherein the memory controller is further configured to: receive a write request from a host, determine a target zone indicated by the write request among the plurality of zones, and determine a logical address of the target zone on which a write operation is to be started based on a write pointer and an offset corresponding to the target zone.
Pulse amplitude modulation (PAM) for multi-host support in a memory sub-system
First data is received from a first host system and second data is received from a second host system. A composite signal is generated to represent both the first data received from the first host system and the second data received from the second host system. The composite signal comprises a series of signal pulses at multiple levels. A first level and a second level in the composite signal represent values from the first data received from the first host system. A third level and a fourth level in the composite signal represent values from the second data received from the second host system. The composite signal is provided to the memory device.