Techniques discussed herein relate to providing composable edge devices. In some embodiments, a user request specifying a set of services to be executed at a cloud-computing edge device may be received by a computing device operated by a cloud computing provider. A manifest may be generated in accordance with the user request. The manifest may specify a configuration for the cloud-computing edge device. Another request can be received specifying the same or a different set of services to be executed at another edge device. Another manifest which specifies the configuration for that edge device may be generated and subsequently used to provision the request set of services on that device. In this manner, manifests can be used to compose the platform to be utilized at any given edge device.

Example implementations relate to metadata operations in a storage system. An example method includes receiving, from a first stream process, a first write request for a first container index in memory. The method further includes, in response to a receipt of the first write request, sending a first token to the first stream process without writing the first container index to a persistent storage. The method further includes receiving, from a second stream process, a first completion request for the first container index. The method further includes, in response to a receipt of the first completion request, writing the first container index from the memory to the persistent storage.

A VPU and associated components include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators are used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer is included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU executes a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Embodiments of the present invention provide a system, a method, and an electronic device for the cloud-based configuration of FPGA configuration data. The system includes a control module internal to an FPGA and a storage module external to the FPGA. The storage module is configured to store configuration data transmitted from a cloud, and the control module is configured to retrieve the configuration data from the storage module and to configure a corresponding processing unit of the FPGA according to the configuration data. In the embodiments of the present invention, the control module internal to the FPGA is provided, and configuration data is retrieved from the storage module external to the FPGA to configure the corresponding processing unit of the FPGA. Accordingly, during FPGA data migration, the configuration data stored in the external storage module can be directly migrated by using a general data migration method, thereby implementing live migration of FPGA data.

Examples herein describe hardware architecture for processing and accelerating data passing through layers of a neural network. In one embodiment, a reconfigurable integrated circuit (IC) for use with a neural network includes a digital processing engine (DPE) array, each DPE having a plurality of neural network units (NNUs). Each DPE generates different output data based on the currently processing layer of the neural network, with the NNUs parallel processing different input data sets. The reconfigurable IC also includes a plurality of ping-pong buffers designed to alternate storing and processing data for the layers of the neural network.

According to one embodiment, a memory system includes a volatile memory, a power supply circuit, and a controller. The power supply circuit includes a first power supply path in which power supplied from a host device is supplied to the volatile memory, a second power supply path in which the power is supplied from the internal power supply to the volatile memory, and a switching device that switches between the first power supply path and the second power supply path. In response to an instruction for a transition to a low power consumption mode received from the host device, the controller outputs, to the switching device, an instruction to switch the power supply circuit from the first power supply path to the second power supply path.

A mapping table updating method, a memory control circuit unit and a memory storage device are provided. The mapping table updating method includes: recording first mapping information as a mapping relation between a first virtual block and a first physical erasing unit; recording second mapping information as a mapping relation between the first virtual block and a second virtual block, and the second virtual block is mapped to the first physical erasing unit; and updating the second mapping information as a mapping relation between the first virtual block and a third virtual block if copying data belonging to the first physical erasing unit to a second physical erasing unit, and the third virtual block is mapped to the second physical erasing unit.

Systems and methods for sharing information between a publisher and a subscriber are disclosed. The system includes a shared memory and a memory broker. The memory broker is configured to receive a request for writing a message relating to a topic from a publisher and determine whether a communication channel corresponding to the topic exists in the shared memory. If the communication channel corresponding to the topic exists, the memory broker then assigns a buffer ring on the communication channel to the publisher, transmits information relating to the buffer ring to the publisher, and transmits information relating to the buffer ring to one or more subscribers of the communication channel.

The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.

A memory controller connectable to a semiconductor memory including a plurality of memory areas, includes a counter circuit configured to count a degree of wear of each of the memory areas in response to a memory operation addressed thereto, and a control circuit configured to set a rate of for wear leveling to be performed on the plurality of memory areas based on a total number of memory operations performed thereon, and select whether to perform wear leveling on each of the memory areas based on the rate, the degree of wear counted for the memory area, a first threshold for the degree of wear, and a second threshold for the degree of wear. The second threshold is greater than the first threshold.