An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

The present disclosure provides a method of data protection for a NAND memory. The method includes programming first and second pages of a NAND flash memory device according to programming data such that data stored in the first and second pages are redundant. The programming of the first and second pages includes a plurality of programming operations using a plurality of programming voltages and a plurality of verifying operations to determine whether programmed memory cells of the first page have threshold voltage levels according to the programming data. The method also includes determining a completion of the programming of the first and second pages based on each of the plurality of verification operations returning a pass result. The method also includes performing, after the determining, a read operation on the second page by the NAND flash memory device to self-verify the data stored at the second page.

Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.

Disclosed are various examples of providing efficient bit compression for direct mapping of physical memory addresses. In some examples, a hypervisor operating system component generates a mask of used address space bits indicated by memory map entries for a computing device. A longest range of unused address space bits is identified using the mask. The memory map entries are transformed to omit the longest range of unused address space bits.

An apparatus includes at least one processing device configured to establish a plurality of paths between at least one initiator of a host device and a plurality of targets of respective storage nodes of a distributed storage system, and for each of a plurality of input-output operations generated in the host device for delivery to the distributed storage system: to access a target lookup service of the host device to determine a particular one of the storage nodes that stores data for a logical storage volume and offset targeted by the input-output operation, to select a particular one of the plurality of paths from the initiator to one of the targets on the particular storage node, and to send the input-output operation to the particular storage node over the selected path. The initiator and the targets are illustratively configured in accordance with a designated standard storage access protocol.

A quad-to-single (Q2S) data structure comprising a plurality of the Q2S mapping entries is maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes of the non-volatile memory device with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list. The linked list corresponds to a Q2S mapping entry associated with the QLC block stripe to be programmed.

A method includes calculating, by a data storage device processor, at least one access trajectory from a first disc surface location to at least one second disc surface location at which at least one primary data access operation is to be carried out. The method also includes determining, by the data storage device controller, whether an opportunity to commence at least one secondary data access operation exists along or proximate to the at least one access trajectory from the first disc surface location to the at least one second disc surface location.

A semiconductor memory device may include a memory cell array circuit and a word line driving circuit. The memory cell array circuit may be connected with a plurality of word lines to store data in a program operation. The word line driving circuit may drive a selected word line among the word lines using a program voltage in the program operation. The word line driving circuit may drive each of non-selected word lines adjacent to the selected word line using a step pass voltage including at least two step voltages.

A read-disturb-based read temperature identification system includes storage device(s) that each determine read disturb information for each block in that storage device, use that read disturb information to identify a subset of rows in at least one block in that storage device that have a higher read temperature than the other rows in the at least one block in that storage device and, based on that identification, generate and store a local logical storage element read temperature map that identifies a subset of logical storage elements associated with that storage device that have a higher read temperature than the other logical storage elements associated with that storage device. A global read temperature identification subsystem coupled to the storage device(s) may then retrieve at least a portion of the local logical storage element read temperature map(s) and use them to generate a global logical storage element read temperature map.

An environment and non-transitory computer readable medium that provide runtime write access to a regulated system. A method of providing runtime write access to a regulated system comprising receiving an unauthorized input parameter, and generating a runtime instruction communication. The runtime instruction communication can be modified by an unauthorized function.