Managing starvation in a distributed arbitration scheme including sending, by a starved local arbiter, a starvation message toward a head arbiter, wherein the starvation message comprises an identifier of the starved local arbiter and a request for resources to transfer data to a destination, wherein the requested resources comprise a destination token and a bus slot; receiving, by a neighboring local arbiter, the starvation message, wherein the neighboring local arbiter is between the starved local arbiter and the head arbiter; if the neighboring local arbiter currently has the resources requested in the starvation message: marking, by the neighboring local arbiter, the requested resources with the identifier of the starved local arbiter.

A number of software routines comprising at least two software routines are created for an interface unit of a computer system having a first and a second interface processor for forwarding input data from a peripheral to a processor of the computer system on which software is programmed. A first subset of the software routines is assigned to a first category provided for task-synchronous data transfer, and a second subset of the software routines are assigned to a second category provided for continuous data transfer. The first interface processor is programmed with the first subset and the second interface processor with the second subset of software routines. During execution of the software, the first subset is cyclically executed by the first interface processor at a first cycle rate, and the second subset is cyclically executed by the second interface processor at a second cycle rate.

Examples include a method of compensating for hold-over errors in a distributed clock synchronization system. When a first computing platform has a synchronized connection with a second computing platform, a clock sync component obtains a first temperature of a network input/output (I/O) device of the first computing platform and a frequency adjustment value of a clock of the network I/O device and stores the temperature and the frequency adjustment value in an entry in a clock synchronization database. When the first computing platform does not have a synchronized connection with the second computing platform (e.g., hold-over mode), the clock sync component obtains a second temperature of the network I/O device, searches the clock synchronization database for the entry where the first temperature is closest to the second temperature, and when the entry is found, obtains the frequency adjustment value and adjusts the clock of the network I/O device using the frequency adjustment value.

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.

Aspects relate to lane failure recovery for a data link having multiple lanes labeled in a contiguous sequence. In one aspect, a failure of a failed lane of the data link is detected. Working lanes of the data link are then detected. A set of contiguous working lanes of the data link are selected, and an operational link as including the selected set of contiguous working lanes is defined. A start address of the operational link is identified and stored in a configuration register. Data traffic is transmitted on the operational link.

Method for managing the state of buttons of peripheral devices of computers of any type (including smartphones, tablets, etc.) is considered in the context of safe management by the corresponding segment of the user interface in the automatic or remote mode without direct tactile communication with the user, but at his desire. Manipulation with buttons on peripheral devices is carried out by the button state change agent which is built in directly the peripheral device who in turn is controlled on the channel of interaction of the computer and the peripheral device means of the software of the computer. Based on the technical result of using appropriately implemented additional user interfaces are also claimed methods of remote management of the computer, interactions between applications and also implementations of the answering machine, PBX and the VoIP-Cell gateway on the basis of smartphones.

According to certain implementations, a motherboard is provided that enables operation as either multiple independent single-processor systems or a single multiple-processor system. In response to a request to configure the motherboard as multiple independent single-processor systems, a control block is implemented for each processor attached to the motherboard, where the control blocks configure the processors to boot and operate independently of each other, and the processors utilize separate motherboard resources. In response to a request to configure the motherboard as multiple independent single-processor systems, a single control block is implemented all processors attached to the motherboard, where the single control block configures all processors to boot and operate in a connected state, and the processors share all motherboard resources.

A location-based address adapter for use in a system to facilitate communication between a host computer and one peripheral device of a plurality of peripheral devices includes a body and an electrical circuit. The body is removably attached to one peripheral device at a time. The electrical circuit includes a communications interface circuit and an adapter memory circuit. The communications interface circuit has a respective pass-through wired connection between each of a plurality of input connectors and a plurality of output connectors to facilitate bi-directional communications between the host computer and the peripheral device. The adapter memory circuit stores a unique physical location address for association with a physical location associated with the peripheral device to which the body is attached. The unique physical location address is a non-network based address. The memory circuit has a memory connector to facilitate direct electrical communicative connection only with the respective peripheral device.

A location-based address adapter for use in a system to facilitate communication between a host computer and one peripheral device of a plurality of peripheral devices includes a body and an electrical circuit. The body is removably attached to one peripheral device at a time. The electrical circuit includes a communications interface circuit and an adapter memory circuit. The communications interface circuit has a respective pass-through wired connection between each of a plurality of input connectors and a plurality of output connectors to facilitate bi-directional communications between the host computer and the peripheral device. The adapter memory circuit stores a unique physical location address for association with a physical location associated with the peripheral device to which the body is attached. The unique physical location address is a non-network based address. The memory circuit has a memory connector to facilitate direct electrical communicative connection only with the respective peripheral device.