A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.

Remote direct memory access (RDMA) enables access to a memory resource on a computing device without involving the device's CPU (central processing unit). Data packets traversing a NIC (network interface controller/card) on a server in a network are efficiently captured by adapting an ASIC (application-specific circuit) in a programmable TOR (top of rack) switch to modify headers of incoming data packets to indicate to the NIC that the packets are RDMA packets. Such modification enables the packets to be written directly to the server memory while bypassing the server's CPU which can typically act as a bottleneck when attempting full packet capture.

A method of managing an external device includes obtaining parameter information of the external device, loading a service module according to the parameter information of the external device, and enabling a communication between a user interface module and a network interface corresponding to the service module.

A switch is described. The switch includes a plurality of ports, a plurality of port logic modules, a memory, and a switch fabric. Transactions ingress and egress the switch via the ports. The port logic modules are coupled with the ports. Each port logic module has core clock domain logic for a core clock domain specific to a corresponding port. The memory includes banks. The memory and the switch fabric have a system clock domain. The core clock domain for each of the port logic modules is different from the system clock domain.

System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

In accordance with various implementations, a method is performed at a data plane node with one or more processors, non-transitory memory, and a control interface between a network function module associated with the data plane node and a switch associated with the data plane node. The method includes determining whether an offload capability is available for a data flow received at an ingress network interface of the data plane node. The method also includes determining whether the data flow satisfies offload criteria in response to determining that the offload capability is available. The method includes bypassing the network function module associated with the data plane node and providing the data flow to at least one of the switch associated with the data plane node or an egress network interface associated with the data plane node in response to determining the offload capability is available and the offload criteria is satisfied.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative memory interface circuit comprises: a plurality of registers storing a plurality of tables, a state machine circuit, and a plurality of queues. The plurality of tables include a memory request table, a memory request identifier table, a memory response table, a memory data message table, and a memory response buffer. The state machine circuit is adapted to receive a load request, and in response, to obtain a first memory request identifier from the load request, to store the first memory request identifier in the memory request identifier table, to generate one or more memory load request data packets having the memory request identifier for transmission to the memory circuit, and to store load request information in the memory request table. The plurality of queues store one or more data packets for transmission.

Described are platforms, systems, and methods for processing a chain of operations through an input output (IO) subsystem without central processing unit (CPU) involvement. In one aspect, a computer-implemented method comprises: providing, via the CPU, the chain of operations to the IO subsystem, wherein the IO subsystem is coupled to the one or more processors over Peripheral Component Interconnect Express (PCIe); processing, with the IO subsystem, the chain of operations by: retrieving, from a memory, data associated with the chain of operations; executing each of the operations in the chain to determine an output based on the data and output determined for any prior executed operation in the chain; and providing the output of each the executed operations for execution of the respective next operation in the chain; and providing, via the IO subsystem, an output for the chain of operations to the CPU.

A communication control device, includes a memory; and a processor coupled to the memory and the processor configured to: store, in the memory, instructions of standby processing in a specific processing order, when a network coupling is being established to perform communication, acquire a specific instructions, update, in the memory, the instructions of standby processing based on a type of the specific instructions, a type of the instructions of standby processing and a relationship specified by order in which the specific instructions are acquired, and after an establishment of the network coupling is completed, perform the instructions of standby processing in a specific processing order.

A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.