Systems and methods are provided that may be implemented to wake an information handling system from a reduced-powered state in response to a wireless signal wake-up event received from a wireless peripheral device. Non-operating system (OS) components and/or non-BIOS components of an information handling system may be optionally enabled to securely perform pre-OS operations to determine whether or not to wake other components (e.g., such as a system OS and/or system BIOS executing on a host processing device or embedded controller) of the information handling system from a reduced-powered state upon receipt of the wireless signal wake-up event.

Devices for coordinating or establishing a direct memory access for a network interface card to a graphics processing unit, and for a network interface card to access a graphics processing unit via a direct memory access are disclosed. For example, a central processing unit may request a graphics processing unit to allocate a memory buffer of the graphics processing unit for a direct memory access by a network interface card and receive from the graphics processing unit a first confirmation of an allocation of the memory buffer. The central processing unit may further transmit to the network interface card a first notification of the allocation of the memory buffer of the graphics processing unit, poll the network interface card to determine when a packet is received by the network interface card, and transmit a second notification to the graphics processing unit that the packet is written to the memory buffer.

Presently disclosed are systems and methods for generating customized filtered-and-partitioned market-data feeds. In an embodiment, an output-feed profile is maintained in data storage at a market-data-processing device (MDPD). The output-feed profile specifies a subset of ticker symbols and a ticker-symbol-based feed-partitioning scheme. An input feed of order-book updates to ticker symbols is received at the MDPD from an upstream device. At the MDPD, a customized market-data output feed is generated according to the maintained output-feed profile at least in part by filtering the input feed down to the order-book updates to ticker symbols in the specified subset and partitioning the filtered feed according to the specified ticker-symbol-based feed-partitioning scheme. The customized market-data output feed is transmitted from the MDPD to a downstream device.

In one embodiment, a network interface controller (NIC) includes multiple packet transmission queues to queue data packets for transmission. The data packets are assigned to multiple traffic classes. The NIC also includes multiple input/output (I/O) interfaces for retrieving the data packets from memory. Each I/O interface is assigned to a subset of the traffic classes. The NIC also includes scheduler circuitry to select a first data packet to be retrieved from memory, and direct memory access (DMA) engine circuitry to retrieve the first data packet from memory via one of the I/O interfaces based on the traffic class of the first data packet, and store the first data packet in one of the packet transmission queues. The NIC also includes a transmission interface to transmit the first data packet over a network at a corresponding launch time indicated by the scheduler circuitry.

A buffer (32) for temporarily storing a packet is installed in a packet order control circuit (12H). A comparison circuit (31) compares the packet ID of an input packet with a next-selection ID indicating the packet ID of a packet to be selected next in accordance with an order. If the comparison result indicates that the packet ID and the next-selection ID do not match, a control circuit (36) stores the input packet in a storage position corresponding to the packet ID. If the packet ID and the next-selection ID match, the control circuit (36) selects the input packet as a target of a transfer process without storing the packet in the buffer (32). If the next-selection ID matches the packet ID of a packet stored in the buffer (32), the control circuit (36) selects the packet as a target of the transfer process. This guarantees the packet processing order with few memory resources.

A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.

In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.

An interconnect module (ICM) having at least two internal data paths is provided. The ICM determines if a connected network interface card (NIC) supports a division of work between the NIC and the ICM. NICs may be standard NICs, advanced NICs (ANICs), or smart NICs (SNICs). The ICM may perform a different amount of processing for network packets received from different devices based on the division of work previously identified. Some NICs may preprocess network packets with respect to switching and routing processing to allow the ICM to bypass that functionality for those packets. Packets received from devices not providing a division of work receive full processing including switching and routing processing. Devices may be grouped to either a switching and routing group or a virtual bypass group such that data received from devices associated with the virtual bypass group may bypass selected processing typically performed by the ICM.

An apparatus comprising a socket insert that is arranged in a receptacle of the apparatus. The socket insert is connected to an operating medium connector. In the receptacle a data interface is covered by the socket insert and inaccessible from outside. To obtain access to the apparatus software or data, the socket insert can be replaced by a service insert that covers the operating medium output but contacts the data plug. The service insert allows communication with the apparatus control to input or output data and/or programs. The arrangement of the service interface covered by socket inserts provides an effective means for access control to the service interface. It impedes or avoids non-authorized access to the interface and damages for persons and material that otherwise could occur due to the missing disruptive discharge proof potential separation between the service interface and particularly the power section of the apparatus control.

A smart network interface card (SNIC) is provided. The SNIC may connect to an interconnect module (ICM) having at least two internal data paths. The SNIC and ICM determine a division of work between them. In general, NICs may be standard NICs, advanced NICs (ANICs), or smart NICs (SNICs). The ICM may perform a different amount of processing for network packets received from different devices based on the division of work previously identified. Some SNICs may preprocess network packets with respect to switching and routing processing to allow the ICM to bypass that functionality. Packets received from devices providing a division of work (e.g., SNICs) may receive reduced processing for functions offloaded to the SNIC. SNICs may utilize either a switching and routing group or a virtual bypass group such that data may bypass selected processing typically performed by the ICM.