Patent classifications
G06F13/366
Atomic Instruction Set and Architecture with Bus Arbitration Locking
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to identify a first input instruction in a code stream to be executed, determine that the first input instruction includes an atomic operation designation, and selectively block interrupts for a duration of execution of the first input instruction and a second input instruction. The second input instruction is to immediately follow the first input instruction in the code stream.
Atomic Instruction Set and Architecture with Bus Arbitration Locking
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to identify a first input instruction in a code stream to be executed, determine that the first input instruction includes an atomic operation designation, and selectively block interrupts for a duration of execution of the first input instruction and a second input instruction. The second input instruction is to immediately follow the first input instruction in the code stream.
Configurable input/output device and operation method thereof
A configurable input/output device includes a plurality of input/output terminals, a routing module, and a first universal input/output channel. The input/output terminals are connected a plurality of field devices. The input/output terminals receive a plurality of input signals from the field devices, and output a plurality of output signals to the field devices. At least two of the input signals are different, at least two of the output signals are different, and at least two the field devices are different. The routing module is connected to the input/output terminals. The first universal input/output channel is connected to the routing module. The routing module controls connections between the first universal input/output channel and the input/output terminals. The routing module also controls the transceiving sequence for the input signals and the output signals.
Configurable input/output device and operation method thereof
A configurable input/output device includes a plurality of input/output terminals, a routing module, and a first universal input/output channel. The input/output terminals are connected a plurality of field devices. The input/output terminals receive a plurality of input signals from the field devices, and output a plurality of output signals to the field devices. At least two of the input signals are different, at least two of the output signals are different, and at least two the field devices are different. The routing module is connected to the input/output terminals. The first universal input/output channel is connected to the routing module. The routing module controls connections between the first universal input/output channel and the input/output terminals. The routing module also controls the transceiving sequence for the input signals and the output signals.
On-circuit data activity monitoring for a systolic array
On-circuit data activity monitoring may be performed for a systolic array. A current data activity measurement may be determined for changes in input data for processing at a systolic array and compared with a prior data activity measurement. Based on the comparison, a throttling recommendation may be provided to a management component to determine whether to perform the throttling recommendation.
On-circuit data activity monitoring for a systolic array
On-circuit data activity monitoring may be performed for a systolic array. A current data activity measurement may be determined for changes in input data for processing at a systolic array and compared with a prior data activity measurement. Based on the comparison, a throttling recommendation may be provided to a management component to determine whether to perform the throttling recommendation.
SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION BUS ARBITRATION
A system and method for efficient communication bus arbitration in a communication protocol are provided. The system and method for efficient communication bus arbitration are a system and method for slave communication bus arbitration in multi-drop communication, and provide efficient and fast communication speed by improving the packet structure in a manner in which a slave controller sequentially responds to a query of a master controller.
SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION BUS ARBITRATION
A system and method for efficient communication bus arbitration in a communication protocol are provided. The system and method for efficient communication bus arbitration are a system and method for slave communication bus arbitration in multi-drop communication, and provide efficient and fast communication speed by improving the packet structure in a manner in which a slave controller sequentially responds to a query of a master controller.
Interrupt controller for controlling interrupts based on priorities of interrupts
The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.
Interrupt controller for controlling interrupts based on priorities of interrupts
The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.