A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.

A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

A system and method for efficient communication bus arbitration in a communication protocol are provided. The system and method for efficient communication bus arbitration are a system and method for slave communication bus arbitration in multi-drop communication, and provide efficient and fast communication speed by improving the packet structure in a manner in which a slave controller sequentially responds to a query of a master controller.

A system and method for efficient communication bus arbitration in a communication protocol are provided. The system and method for efficient communication bus arbitration are a system and method for slave communication bus arbitration in multi-drop communication, and provide efficient and fast communication speed by improving the packet structure in a manner in which a slave controller sequentially responds to a query of a master controller.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

An arbiter may include a plurality of cells, mapping logic, a fixed priority arbiter, and unmapping logic. Each cell may be associated with a corresponding client and configured to store a priority for the corresponding client. The mapping logic may be connected to the plurality of cells to order requests received from the clients according to the priorities stored in the cells. The fixed priority arbiter may receive the ordered requests and generate a grant for a winning request of the requests. The unmapping logic may use the stored priorities to yield the grant back to the winning client that sent the winning request.

An arbiter may include a plurality of cells, mapping logic, a fixed priority arbiter, and unmapping logic. Each cell may be associated with a corresponding client and configured to store a priority for the corresponding client. The mapping logic may be connected to the plurality of cells to order requests received from the clients according to the priorities stored in the cells. The fixed priority arbiter may receive the ordered requests and generate a grant for a winning request of the requests. The unmapping logic may use the stored priorities to yield the grant back to the winning client that sent the winning request.

The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.