A data bus includes process elements and a linear main pipeline. Each process element is coupled to a linear pipeline having M stages arranged in series, each of the M stages including a buffer element configured to buffer a data bit sequence and to forward the buffered data bit sequence from a first of the buffer elements to a last of the buffer elements. The linear main pipeline includes N pipeline stage elements arranged in series. Each pipeline stage element is connected to the last buffer element of a respective linear pipeline and configured to read-out one or more of the buffered data bit sequences and to forward the read-out data bit sequences from one of N pipeline stag elements to a next of the N pipeline stage elements.

An embodiment of the present invention relates to physical interfaces, especially those used on consumer electronics devices. A processor, in which an embodiment of the disclosed invention is deployed, includes a physical interface for connecting to and communicating with a peripheral device, the peripheral device being configured to operate according to a standard communications protocol or to a different protocol which is adapted to have a more bandwidth-efficient performance. The processor detects which of the two protocols the attached peripheral device uses and configures the physical interface to operate according to the detected protocol. An embodiment of the invention allows for new, bandwidth-efficient communications protocols to be executed across existing standardized physical interface hardware, thereby allowing for easier acceptance of the new protocols within the consumer electronics industry. Bandwidth-efficient communications protocols advantageously allow for more convenient transfer of media content or for big-data applications to be more conveniently handled.

A data bus includes process elements and a linear main pipeline. Each process element is coupled to a linear pipeline having M stages arranged in series, each of the M stages including a buffer element configured to buffer a data bit sequence and to forward the buffered data bit sequence from a first of the buffer elements to a last of the buffer elements. The linear main pipeline includes N pipeline stage elements arranged in series. Each pipeline stage element is connected to the last buffer element of a respective linear pipeline and configured to read-out one or more of the buffered data bit sequences and to forward the read-out data bit sequences from one of N pipeline stag elements to a next of the N pipeline stage elements.

Techniques are disclosed for hot swapping one or more module devices on a single host device. A module device can perform module-specific tasks that are defined in its module software driver. Using one or more application programming interfaces, the host device communicates with the module device's module software driver to allow the module device to perform module-specific tasks while removably connected to the host device.

An embodiment of the present invention relates to physical interfaces, especially those used on consumer electronics devices. A processor, in which an embodiment of the disclosed invention is deployed, includes a physical interface for connecting to and communicating with a peripheral device, the peripheral device being configured to operate according to a standard communications protocol or to a different protocol which is adapted to have a more bandwidth-efficient performance. The processor detects which of the two protocols the attached peripheral device uses and configures the physical interface to operate according to the detected protocol. An embodiment of the invention allows for new, bandwidth-efficient communications protocols to be executed across existing standardized physical interface hardware, thereby allowing for easier acceptance of the new protocols within the consumer electronics industry. Bandwidth-efficient communications protocols advantageously allow for more convenient transfer of media content or for big-data applications to be more conveniently handled.

Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

A method includes generating, by a control unit of a first device, a handshaking signal to be transmitted to a second device via a second channel. The method further includes based on the handshaking signal being acknowledged by the second device, configuring, by the control unit, the second channel to communicate non-display data and configuring a first channel connecting the first device to the second device to selectively communicate either display data or non-display data; and based on the handshaking signal being not acknowledged by the second device, configuring, by the control unit, the first channel to communicate display data.

A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.

An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a command signal and creates data transmission link to the computer device. The master storage unit has at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to transmit the command signal from the master storage unit to the slave storage unit.