Supply of a first clock signal used in an interface part of each of a plurality of slave devices on a ring bus and a second clock signal used in a core part of each of the plurality of slave devices is controlled. The slave device as the target of a request issued from a master device is specified. The first clock signal is supplied to each of the plurality of slave devices and the second clock signal is supplied to the specified slaved device.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation. Several fringe timing points are sampled, whereby several of the plurality of fringe timing points are associated with each of the transition edges of the second stream of data bits input to the data interface circuit. The drift amount is compared with a drift correction threshold value and the first optimal sampling point is shifted in time by the drift amount to revise the first optimal sampling point.

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

A method of transferring control data between a master device and a slave device over a path including at least one intermediate device, such that the path includes multiple path segments between successive pairs of devices. Data is transferred on each path segment in a plurality of frames of data, wherein the frames are synchronized between said path segments. The control data is transmitted in command slots of each frame, wherein a command slot comprises a set of control data bit slots, and wherein a control data bit slot is a time window associated with the transfer of a single control data bit over a single path segment between the devices on the path segment. The control data bit slots for each command slot are subdivided into: a first set of bit slots reserved for the transfer of control data in the direction from the master device to the slave device, and a second set of bit slots reserved for the transfer of control data either in the direction from the master device to the slave device or in the direction from the slave device to the master device. The time positions of the command slots on each path segment are offset from the positions of the command slots on each respective adjacent path segment by at least one control data bit slot.

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and output registered C/A signals and buffer control signals. The memory module further comprises a plurality of buffer circuits. In response to the buffer control signals, each buffer circuit is configured to communicate first data/strobe signals with at least one memory device and to communicate second data/strobe signals with the memory controller. The buffer circuit includes at least one delay circuit configured to delay at least one signal of the first data/strobe signals based on a first delay and a second delay. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices that includes at least one corresponding memory device in each of the one or more ranks.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method and a first set of values is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, establishing a second set of values. Several fringe timing points are sampled. A drift amount is compared with a drift correction threshold value and the first optimal sampling point is shifted in time by the drift amount to revise the first optimal sampling point.

Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.