An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

An apparatus may include one or more registers configured to store a plurality of values, and an analog-to-digital converter (ADC). Each value of the plurality of values may correspond to a characteristic of a transistor at a respective temperature value. The ADC may be configured to generate a digital value corresponding to a difference in voltage levels between a first terminal and a second terminal of the transistor. The apparatus may further include a sensor configured to measure a temperature, and control logic configured to generate a first voltage level at a control terminal of the transistor and receive the digital value from the ADC. The control logic may be further configured to determine, during a first operational mode, a current passing through the transistor dependent upon the digital value, at least one value of the plurality of values, and the temperature.

Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

In a communications assembly having multiple users, one user is designated as a master and additional users are designated as peripheral modules, at least two of the peripheral modules as well as at least two interface modules are integrated into a shared physical implementation unit, and at least one interface module, which is designated as a slave, is unambiguously assigned to each of the at least two peripheral modules.

A signal processing circuit includes: a plurality of daisy chain-connected AD converters each including a data ready output terminal, a synchronizing signal input terminal, and a serial clock input terminal; a calculator connected to the data ready output terminal of any of the AD converters and for outputting a serial clock to the serial clock input terminal of each of the AD converters when a data ready signal is input; and a reset processor included in the calculator and for outputting a synchronizing signal to the synchronizing signal input terminal of each of the AD converters when an output time lag among data ready signals from each of the AD converters is detected for a predetermined number of times.

An apparatus may include an energy monitoring circuit configured to generate a bitstream dependent upon an amount of charge passing through a sensing unit. The apparatus may also include a control unit configured to receive the bitstream from the energy monitoring circuit, and modify a count value in response to a determined state of each bit of the bitstream. The control unit may also read a first value of the count value at a first time and at a later second time read a second value of the count value. The control unit may assert a wake-up signal in response to a determination that a difference between the first value and the second value is greater than a predetermined threshold value.

Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.