Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

A bus configuration system includes a plurality of driver integrated circuits (ICs) coupled sequentially on a daisy chain, and a bus controller coupled to the plurality of driver ICs. Each driver IC includes a plurality of ports. The bus controller is used to generate a port definition code for configuring each port of the each driver IC. The bus controller includes a clock output port used to output a clock signal and a data output port used to output a data signal. When a port of the plurality of ports detects the clock signal, the port is configured as a clock input port.

A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

An electronic circuit system includes a main device that generates first and second strobe signals and a clock signal, a first peripheral device that uses the first strobe signal to generate a first output signal in a first lane in response to the clock signal, and a second peripheral device that uses the second strobe signal to generate a second output signal in a second lane in response to the clock signal. The main device determines if the first peripheral device is coupled to the main device through the first lane based on the first output signal. The main device determines if the second peripheral device is coupled to the main device through the second lane based on the second output signal. The main device also has the ability to detect if a peripheral device is faulty and to select a valid configuration of peripheral devices.

A serial peripheral interface system with a slave expander method and apparatus can include: receiving a data stream from a master device, the data stream beginning with an address; decoding the address as the data stream is being received; activating an independent slave select after the address is decoded and before a second portion of the data stream is received; and deactivating the independent slave select based on a slave select from the master device being deactivated.

A home node of a data processing apparatus that includes a number of devices coupled via an interconnect system is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and the data bus width of the interconnect system. Data is transferred as a cache line serialized into a number of data beats. The home node may be configured to minimize the number of data transfers on the third data bus or to minimize latency in the transfer of the critical beat of the cache line.

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

A home node of a data processing apparatus that includes a number of devices coupled via an interconnect system is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and the data bus width of the interconnect system. Data is transferred as a cache line serialized into a number of data beats. The home node may be configured to minimize the number of data transfers on the third data bus or to minimize latency in the transfer of the critical beat of the cache line.

A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.

The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.