A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port; and the queue is stored in a second buffer; recording a storage duration of each packet stored in the first buffer, and accumulating the storage duration of each packet stored in the first buffer; removing the packet from the first buffer after the packet is transmitted via the PCIe port; and generating an indication of packet pressure at the PCIe port based on the accumulated storage duration.

Apparatus and method relate to a data channel. In this apparatus, an input circuit is configured to gate a valid input with a ready output to provide a forward token (f-token) to a first f-token register of a f-token pipeline and to a counter, and to receive data to a first data register of a data pipeline. An output circuit is configured to gate a ready input with a valid output to provide a return token (r-token) to a first r-token register of a r-token pipeline and to a FWFT FIFO, to receive the f-token from a second f-token register of the f-token pipeline to the FWFT FIFO, and to receive the data from a second data register of the data pipeline to the FWFT FIFO. The input circuit receives the r-token from the first r-token register to a second r-token register of the r-token pipeline for the counter.

An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.

A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.

This disclosure concerns an apparatus of multiple processors, such as microprocessors and communications therebetween and enables efficient half-duplex two-way communication between two processors, each having two logic output pins and two logic input pins, e.g. GPIO pins, available for the communication. For each of the first and the second processor (101, 102), the first logic output pin (11, 21) is connected to the second logic input pin (14, 24) of the respective other processor (101, 102), and for each of the first and the second processor (101, 102), the second logic output pin (12, 22) is connected to the first logic input pin (13, 23) of the respective other processor (101, 102). Each of the first and the second processor (101, 102) is operable in a transmit mode by controlling the second logic output pin (12, 22) and in a receive mode by determining a sequence of data bits (D7-D0) from the logic data signal (DAT) received on the first logic input pin (13, 23) in response to state transitions of the logic clock signal (CLK) received on the second logic input pin (14, 24).

In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels.

In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

A data transfer system, a method of data transfer and a corresponding transmitter and receiver are disclosed. A communication protocol between the transmitter and receiver is defined using a set of valid transmission states for communication from the transmitter to the receiver and a set of valid acknowledgement states for transmission from the receiver to the transmitter. A Hamming distance between patterns of zeroes, and between patterns of ones, in valid states of each of these sets is at least one and the transmitter is arranged to transition between a number of transmission states in response to the reception of an acknowledgement state from the receiver which matches a transmission state it has sent to the receiver on a request bus. A communication protocol which is robust across a multi-voltage and/or clock domain interface is thus provided.

A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port; and the queue is stored in a second buffer; recording a storage duration of each packet stored in the first buffer, and accumulating the storage duration of each packet stored in the first buffer; removing the packet from the first buffer after the packet is transmitted via the PCIe port; and generating an indication of packet pressure at the PCIe port based on the accumulated storage duration.