An integrated circuit device includes a circuit device main body which is configured to execute a predetermined processing function, a communication control circuit which is configured to perform data communication with an external control device and an operation mode determination unit which is configured to selectively determine a normal mode for executing the processing function or a debug mode for setting an execution condition of the processing function as an operation mode of the circuit device main body. The operation mode determination circuit is configured to operate in accordance with an internal clock and to generate an operation mode output value for determining the operation mode of the circuit device main body according to a logical state of a particular one communication signal which is data-communicated with the external control device after a reset operation performed by a reset circuit is released.

The invention concerns an apparatus comprising multiple processors, such as microprocessors, that communicate with each other. The claimed apparatus provides communication between two or more processors, such as microprocessors, and enables efficient half-duplex two-way communication between two processors, each having only two logic output pins and two logic input pins, e.g. GPIO pins, available for the communication.

The apparatus (109) comprises a first processor (101) and a second processor (102), each having a first logic output pin (11, 21), a second logic output pin (12, 22), a first logic input pin (13, 23) and a second logic input pin (14, 24). For each of the first and the second processor (101, 102), the first logic output pin (11, 21) is connected to the second logic input pin (14, 24) of the respective other processor (101, 102), and for each of the first and the second processor (101, 102), the second logic output pin (12, 22) is connected to the first logic input pin (13, 23) of the respective other processor (101, 102).

Each of the first and the second processor (101, 102) is operable in a transmit mode (301) for transmitting data to the respective other processor (101, 102) by controlling the second logic output pin (12, 22) to provide a logic data signal (DAT) indicating a sequence of data bits (D7-D0) and controlling the first logic output pin (11, 21) to provide a logic clock signal (CLK) with state transitions indicating when the logic data signal (DAT) indicates the values of the individual data bits (D7-D0) in the sequence.

Each of the first and the second processor (101, 102) is operable in a receive mode (401) for receiving data from the respective other processor (101, 102) by determining a sequence of data bits (D7-D0) from the logic data signal (DAT) received on the first logic input pin (13, 23) in response to state transitions of the logic clock signal (CLK) received on the second logic input pin (14, 24).

The apparatus (109) is characterized in that each of the first and the second processor (101, 102) further is configured to: in dependence on being in the receive mode (401) and able to receive data, control the second logic output pin (12, 22) to provide a logic clear-to-send signal (CTS) indicating the ability to receive data and control the first logic output pin (11, 21) to provide a logic data-acknowledge signal (ACK) with state transitions indicating s

Methods and systems for changing topology of an asymmetric network and operating end-devices coupled to a self-configurable asymmetric network. The self-configurable asymmetric network supports at least two different network topologies and enables: displaying information regarding end-devices that may be accessed via different network topologies, selecting a network topology by setting the direction of a self-configurable asymmetric link, and indicating a subset of the end-devices that are accessible via the selected network topology.

A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.

An enhanced general input/output communication architecture, protocol and related methods are presented.

A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels.

An electronic apparatus of an embodiment includes a first connector including a plurality of terminals including a detection signal output terminal for outputting a detection signal and an identification signal input terminal for receiving an identification signal; a connection cable connecting the detection signal output terminal and the identification signal input terminal to a corresponding terminal of a peripheral apparatus by cross wiring; and a control unit that monitors an input signal of the identification signal input terminal by supplying the detection signal to the detection signal output terminal, and starts signal transmission or electrical power transmission through a remaining terminal in a condition where the identification signal is input to the identification signal input terminal based on the detection signal.

In an embodiment, a host controller is configured to control communication with a plurality of universal serial bus (USB) devices, and to couple to a management controller and a host processor. The host controller includes a filter logic to filter information from a management control transmission protocol (MCTP) endpoint of a first USB device from being communicated to the host processor and to provide the MCTP endpoint information to the management controller. Other embodiments are described and claimed.

An enhanced general input/output communication architecture, protocol and related methods are presented.

A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels.