An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.

Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

A data transmission apparatus includes lanes, a first clock generation circuit, a second clock generation circuit, a first circuit, and a second circuit. The first clock generation circuit can generate a first clock as a reference for data transmission in a first lane. The second clock generation circuit can generate a second clock as a reference for data transmission in a second lane. The first circuit can determine a shift amount by notification of a first delay amount of the first lane and a second delay amount of the second lane to cause a delay amount of one of the first clock and the second clock to match a delay amount of the other of the first clock and the second clock. The second circuit can shift the first delay amount or the second delay amount based on the determined shift amount.

A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.

Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

In an exemplary variable rate display interface, a high-speed reverse data transfer is enabled over plural lanes of a display serial interface (DSI) bus during blanking periods. Further increases in bandwidth of each high-speed reverse data transfer may be achieved by increasing DSI clock speed during the blanking periods. Since a display relies on a host clock to send reverse data, the frequency of the reverse data is increased, which effectively increases the bandwidth of reverse channel lanes. By increasing the reverse bandwidth over existing pins in the DSI bus, more data may be transferred to the host, including raw touch/stylus data rather than processed data. The raw data may then be processed by the host's relatively powerful processors. By shifting the processing to the host, the need for a powerful touch screen controller (TSC) and/or a powerful touch display driver integrated circuit (TDDI) may be avoided.

Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.