A portable storage device includes nonvolatile memory devices to store data, a storage controller, and a bridge chipset. The bridge chipset is connected to a first connector of a host through a cable assembly, detects a resistance of the cable assembly, provides the storage controller with USB type information of the first connector based on the detected resistance, and after a USB connection is established with the host, provides the storage controller with USB version information associated with the established USB connection. The storage controller selects one of a plurality of initializing modes based on the USB type information and the USB version information, selects clock signals having frequencies in a range within a maximum power level, and performs an initializing operation based on the selected clock signals within an internal reference time interval.

The disclosure provides a method for determining link delay. The method includes: according to a preset frequency division multiple, performing frequency division on a first Local Multi Frame Clock (LMFC) of each data lane obtained by parsing to obtain a second LMFC corresponding to each data lane, and, according to the second LMFC, writing respectively the data of each data lane into a corresponding buffer; and according to a SYSREF signal and a preset LMFC interval, generating a third LMFC, and, according to the third LMFC, reading respectively the data of each data lane from the corresponding buffer. The period of the second LMFC is the same as the period of the third LMFC. The disclosure also provides an apparatus, a communication device and a storage medium for implementing the method.

An interconnect controller for a data processing platform includes a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer, and a physical layer controller coupled to the data link layer controller and adapted to be coupled to a communication link. The physical layer controller operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount. In response to performing a link initialization, the interconnect controller performs at least one setup operation to select a speed, and subsequently operates the communication link using a selected speed.

Link speed control systems for power optimization are disclosed. In one aspect, a communication link adjusts a data transfer speed based on link utilization levels. In a second exemplary aspect, one or more conditions affecting a link speed are weighted and collectively evaluated to determine an efficient or optimal link speed. By adjusting the link speed in this fashion, lower link speeds may be used, and net power savings may be effectuated.

A programmable controller according to an embodiment includes: a bus for data transmission and reception; a synchronous-control signal line that transmits a synchronous control signal; a synchronous-control-signal generating unit that is connected to the synchronous-control signal line and generates the synchronous control signal on a basis of an external signal; a data holding unit that is connected to the bus and the synchronous-control signal line and latches a signal from an external device in an internal memory in synchronization with the synchronous control signal; and a CPU unit that is connected to the bus and the synchronous-control signal line and reads a value in the internal memory via the bus in synchronization with the synchronous control signal.

Embodiments discussed herein refer to systems, methods, and circuits for conforming to power up sequencing rules of a conventional hard-wired data connection even though the hard-wired data connection that would ordinarily exist between two data controllers has been replaced with one or more contactless connectors. A consequence of replacing the hard-wired connection with a contactless connector is that the data controllers no longer directly control the power sequencing between the controllers because they are not able to directly communicate with each other over the hard-wired data connections. Power sequence assist circuitry may be used to assists the data controllers in establishing a link in accordance with the power sequencing rules of a particular wired interface despite the intentionally broken hard-wired data connection between the two controllers by instructing the contactless connectors to communicate with their respective data controllers in compliance with the power sequencing rules.

A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.

In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

Communication devices and systems with correct regeneration of an audio signal are disclosed. In one example, a communication device measures a number of predetermined reference clocks included in one cycle of a frequency divided signal, on the basis of an audio master clock having a frequency obtained by multiplying a frequency of a sampling clock to sample an audio signal, a frequency division ratio of a frequency divided signal of the audio master clock, and a predetermined reference clock. A packet generator generates a packet including information including the measured number, a bit width of serial data (SD) conforming to an Inter-IC Sound (I2S) standard, the frequency of the sampling clock, a frequency division ratio of the frequency divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.

A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.