The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. An I3C master receives a max read length and a max write length from an I3C slave. Then, when transmitting/receiving data to/from the I3C slave, the I3C master controls transmission/reception of the data so that the data to be transferred in one data transfer has a data length equal to or shorter than the max read length and the max write length, and transmits transfer length information indicating the data length of the data to be transferred, prior to data transfer of the data. The present technology is applicable to a bus IF, for example.

Techniques for concurrent transmission of audio and ultrasound are described. In an example, a computing device generates, in a digital domain, mixed audio data from multiple sets of audio data, each set corresponding to a different audio channel. The computing device also generates, in the digital domain, ultrasound data, and generates serial data by providing the mixed audio data and the ultrasound data as different inputs to an I2S mixing module. In an analog domain, the computing device generates an output signal based at least in part on the serial data, and sends the output signal to a speaker.

A data transmission method according to an I2C protocol and a transmission apparatus includes: a first transmission chip obtains I2C data from a first device, wherein the I2C data is data sent by the first device to a second device. The first transmission chip sends first feedback information to the first device, wherein the first feedback information is used to indicate whether the I2C data is successfully received. The first transmission chip forwards the I2C data to a second transmission chip corresponding to the second device. The first transmission chip receives second feedback information from the second transmission chip, and the second feedback information is used to indicate whether the I2C data is successfully received. The first transmission chip stores the second feedback information in a first storage space that is storage space of the first transmission chip.

Communication is performed more reliably. A CCI (I3C DDR) processing section determines status of an index when requested to be accessed by an I3C master for a read operation. An error handling section then controls an I3C slave 13 to detect occurrence of an error based on the status of the index and to neglect all communication until DDR mode is stopped or restarted by the I3C master, the I3C slave 13 being further controlled to send a NACK response when performing acknowledge processing on a signal sent from the I3C master. This technology can be applied to the I3C bus, for example.

A microphone array includes a four-channel serial peripheral interface, a core logic unit, a data receiving unit and a voice recognition unit. The four-channel serial peripheral interface includes a bit clock signal line, a frame clock signal line, and four data signal lines, the core logic unit includes a frequency divider module for converting the control signal and the clock signal to provide a bit clock signal and a frame clock signal. The data receiving unit includes a shift register and a buffer, the shift register is connected to four data signal lines and receives input data of the four digital microphones, and the buffer is connected to the shift register. The voice recognition unit is connected to the data receiving unit and receives microphone signals of the four digital microphones to perform voice recognition.

An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

A system timer bus used by the processor elements in an ARM-based system on a chip (SoC) is driven using a Precision Time Measurement (PTM) value. This allows the processor elements to be synchronized to the PCIe ports that use PTM. When two SoCs are connected using PCIe links, this example allows the processor elements in both SoCs to be synchronized. As the processor elements are synchronized, associated tasks on the two SoCs are synchronized, so that overall operations are synchronized.

A host side is adapted to be connected to a client side by means of a clock wire, a selection wire, a first data wire and a second data wire. The host side is configured to transmit a digital selection signal over the selection wire to the client side, the selection signal determining either an audio transmission mode or a client communication mode. Further, the host side is configured to transmit digital audio data of a first channel and a second channel over the first and the second data wire to the client side in the audio transmission mode, and to perform client communication over the first and the second data wire in the client communication mode.