A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.

The technology disclosed herein pertains to a system and method for providing the ability for a computational storage device (CSD) to understand data layout based upon automatic detection or host identification of the file system occupying a non-volatile memory express (NVMe) namespace, the method including receiving, at a CSD, a request to process a file using a computation program stored on the CSD, detecting a filesystem associated with the file within a namespace of CSD, mounting the filesystem on the CSD, interpreting a data structure associated with the file within the namespace, and reading the physical data blocks associated with the file into a computational storage memory (CSM) of the CSD.

According to an embodiment of the disclosure, an electronic device comprises: a battery, a memory, a connector including one or more signal terminals, a first converter included in a first path that connects the battery to the connector, a second converter included in second path that is distinct from the first path and connects the battery to the connector, and a processor electrically connected to the battery, the memory, the connector, the first converter, and the second converter, wherein the memory stores instructions that, when executed, cause the processor to obtain identification information of the external electronic device when the electronic device is connected to the external electronic device through the connector, determine whether the identification information matches comparison data stored in the memory, determine whether a voltage of a power terminal (vbus) among the one or more signal terminals satisfies a specified condition when the identification information matches the comparison data, and transmit power determined based on a real-time voltage of the battery to the external electronic device by using the second path through the connector, based on whether the specified condition is satisfied.

A transceiver device for a user station of a serial bus system, a communication control device, and a method. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus of the bus system, a reception module for receiving the signal from the bus, the reception module being designed to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place as a result of the operating mode changeover signal.

A transceiver device, communication control device, and method for a user station of a serial bus system. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus, a reception module for receiving the signal from the bus, the reception module configured to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place based on the operating mode changeover signal. The changeover feedback block is configured to output the feedback to the communication control device via the second terminal and in the digital reception signal.

Disclosed herein is a universal serial bus port controller on a source side. The universal serial bus port controller is compatible with universal serial bus Type-C. A source is equipped with the universal serial bus port controller including a power supply terminal, a power supply circuit, a switch connected between an output of the power supply circuit and the power supply terminal, a capacitor connected to the power supply terminal, and a discharge resistance and a discharge switch connected in series with each other between the power supply terminal and a ground line. The universal serial bus port controller includes an abnormality detector which detects an output voltage of the power supply terminal a plurality of times after the discharge switch is turned on and detects an abnormality on the basis of a temporal change in the output voltage.

A method for providing more than one function to pins of a programmable device used in a server system includes the programmable device and first and second devices. The programmable device is electrically connected to the first device and the second device. The programmable device includes a major logic communication device, a detection module, a storage module, and at least one multiplexing pin. The second device is powered on, sending an in-position signal to the detection module through the at least one multiplexing pin. The detection module transmits the in-position signal to the storage module. The major logic communication module communicates with the first device through the at least one multiplexing pin. A system applying the method are also disclosed.

In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.