A slave device coupled to a master device via a bus and including a serial interface, a code generator circuit, and a control circuit is provided. The serial interface is configured to be coupled to the bus. The code generator circuit is configured to generate a unique code. The control circuit is coupled between the serial interface and the code generator circuit. In a set mode, the control circuit triggers the code generator circuit to generate the unique code. In an operation mode, the control circuit determines whether to perform commands provided by the master device according to the unique code.

Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

In an embodiment a microcontroller includes a processing unit and a deserial-serial peripheral interface (DSPI) module, wherein the deserial-serial peripheral interface module is coupleable to a communication bus configured to operate according to a selected communication protocol, wherein the processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol, calculate, as a function of the user data, a cyclic redundancy check (CRC) value intended for inclusion in the outgoing frame, compose the outgoing frame by including the user data and the calculated CRC value into the outgoing frame, produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame and program a data register of the deserial-serial peripheral interface module with the DSPI frame, and wherein the deserial-serial peripheral interface module is configured to transmit the DSPI frame via the communication bus.

A communication apparatus includes an I.sup.2C logic circuit, an I3C logic circuit, an external terminal, and a switch circuit. The I.sup.2C logic circuit controls communication via a control data bus in accordance with an I.sup.2C (Inter?Integrated Circuit) communication standard. The I3C logic circuit controls the communication via the control data bus in accordance with an I3C (Improved Inter Integrated Circuit) communication standard. The external terminal is coupled to the control data bus. The switch circuit controls coupling between one of the I.sup.2C logic circuit and the I3C logic circuit, and the external terminal.

A system management bus link, a method and apparatus for determining the pull-up resistance thereof, and a device. The system management bus link comprises: a motherboard chip, a first pull-up resistor, and a second pull-up resistor. In the present invention, when resistance values of the first pull-up resistor and the second pull-up resistor satisfy configuring on a system management bus link any number of PSU power supplies that is smaller than or equal to a number threshold, a clock line in the link and a drive current in a data line are between a 0.5-times drive current threshold and a 0.9-times drive current threshold. Thus, the pull-up resistance of a motherboard end is optimized, which reduces the effect on the drive capacity of the number of PSU power supplies on a link, guarantees the drive capacity of the link, and improves link stability.

Provided is a verification system and a verification method for an Ethernet interface chip. The verification system comprises a Reconciliation Sublayer (RS), a Physical Coding Sublayer (PCS), a Physical Medium Attachment (PMA) layer, and a flow control unit connecting the RS and the PMA layer, wherein the PMA layer is provided with a PMA clock and a buffer, the buffer is configured to store data transferred from the PCS, and the PMA clock is configured to control the PMA layer to send the data in the buffer to an Ethernet interface chip to be tested.

A method for a slave device for calibrating an output timing for transmitting data to a master device is provided. The master and slave devices are communicatively coupled via an interface. The method includes: receiving, from the master device, one or more consecutive first signal edges indicating a synchronization event; recovering a reference clock of the master device based on the one or more consecutive first signal edges; transmitting one or more predetermined second signal edges to the master device and generated using the recovered reference clock; receiving, from the master device, data indicating one or more sampled values of the master device for the one or more predetermined second signal edges; and adjusting the output timing based on a comparison of the one or more predetermined second signal edges and the one or more sampled values of the master device for the one or more predetermined second signal edges.

A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

An embodiment method for managing an operation for modifying the content of the memory plane of a memory device coupled to a processing unit, comprises a communication by the processing unit to the memory device of a control of the operation, an execution of the operation by the memory device, and at the end of the operation, a communication by the memory device itself to the processing unit of information indicating the end of the operation.

A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.