A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

The present disclosure provides an arbitration line-based full-duplex SPI communication method. Said method comprises: a communication requester detecting a first arbitration line corresponding to the communication requester and a second arbitration line corresponding to a communication responder, and if both the first arbitration line and the second arbitration line are at a low potential, pulling up the potential of the first arbitration line; when the communication responder detects the first arbitration line is at a high potential, pulling up the potential of the second arbitration line; when the communication requester detects the second arbitration line is at a high potential, determining the communication responder is in a communicating state; the communication requester and the communication responder sending message header data and message text data to each other. The present disclosure solves the problem of the transmission direction and communication flexibility being limited in existing SPI communication.

A low latency retimer and a low latency control method are provided; a physical layer module is provided on each of two opposite sides of the retimer; each physical layer module includes at least one set of signal transceiver units including a signal receiving unit and a signal transmitting unit; the signal receiving unit performs a serial-to-parallel conversion on a first high-speed serial signal to generate a parallel signal, and sends the parallel signal to the signal transmitting unit; the signal transmitting unit performs a parallel-to-serial conversion on the parallel signal, to convert the parallel signal to obtain a second high-speed serial signal, and outputs the second high-speed serial signal. Data paths of the retimer form a loopback structure, and the signal transmitting unit and the signal receiving unit are physically adjacent to each other, which solves the problem of signal transmission delay, and avoids high power consumption.

A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.

The present disclosure relates to a method for controlling a timing controller and a timing controller. The method for controlling the timing controller includes: acquiring a bus address in a bus signal transmitted over an I2C bus, the I2C bus being connected to the timing controller; if the timing controller determining that the bus address matches an address of the timing controller, acquiring data information in the bus signal; acquiring an address of a target function circuit according to the data information; generating and transmitting a query instruction to a memory according to the address of the target function circuit, and receiving switch control data corresponding to the target function circuit fed back by the memory; controlling, according to the switch control data, a switch connected to the target function circuit to be turned on.

An electronic device comprising: a clock pin; at least one data pin; a storage device, configured to store at least one program; a processing circuit, coupled to the clock pin and the data pin. A device ID setting method is performed when the processing circuit executes the program stored in the storage device. The device ID setting method comprises; (a) recording connections between pins between the first electronic device and the second electronic device by the second electronic device; (b) applying the connections as a device ID of the first electronic device by the second electronic device; and (c) setting pins of the first electronic device such that the data pins of the second electronic device are coupled to the data pins of the first electronic device.

Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

A serial interface, such as a serial peripheral interface (SPI), with improved diagnostic coverage is disclosed. The serial interface includes a data verification module that selects an error detection value in response to a mode signal indicating if the transmitting device is in user mode or test mode. For example, the data verification module computes a cyclic redundancy check (CRC) value and selects either the computed CRC value or its inverse based on the mode. The receiving device can determine the mode of the transmitting device based on the error detection value used. The serial interface further includes a read detector for clearing the transmit data buffer after data is read out. The serial interface may further include a loopback circuit for verifying that the data output from an output pin matches the data from the transmit data buffer.

A system and method are provided for interfacing JESD204-to-PCIe communications. The method transceives JESD204 link layer messages with a JESD204 link layer. The method converts between JESD204 link layer messages and PCIe scrambled messages. The method converts between PCIe scrambled messages and PCIe encoded messages. The PCIe encoded messages are transceived at a JESD clock rate. The PCIe encoded messages transceived at the JESD clock rate are buffered and PCIe encoded messages are then transceived at a PCIe clock rate. The PCIe encoded messages at the PCIe clock rate are transceived with a PCIe physical layer. That is, PCIe encoded messages are either transmitted to the PCIe physical layer at the PCIe clock rate (the transmission path), or received from the PCIe physical layer (at the PCIe clock rate) and buffered (the receive path). The system and method also enable conventional JESD link layer-to-JESD physical layer communications.

A system can include a serial, full-duplex, synchronous peripheral communication interface composed of four communication lines that communicatively couple a host processor to an optical sensor, the four communication lines including: a clock (CLK) line; a chip select (CS) line; a host output (MOSI) line; and a sensor output (MISO) line, the MISO line operating according to the following conditions when the CS line is selected: provide a service register data indicating when one or more predetermined conditions have occurred prior to receiving any commands from the host processor; provide a state register data defining the one or more predetermined conditions that occurred; and in response to receiving a command from the host processor received after the service register data and state register data is provided, the command requesting input device operational data, provide the operational data to the host processor.