In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.

A matrix multiplication circuit module and a matrix multiplication method are provided by the embodiments of the present disclosure. The circuit module includes one or more row-column calculation units for realizing row-column multiplication calculation. Each of the row-column calculation units comprises one or more multiplying units and an adding unit. Each of the one or more multiplying unit has an output end connected to an input end of the adding unit. Each of the multiplying units comprises an electrical signal regulating subunit and a load. The electrical signal regulating subunit is configured to regulate a magnitude of an input electrical signal. A multiplication operation is performed by the electrical signal regulating subunit and the load in response to an electrical signal inputted to the multiplying unit. The load has a fixed load value.

A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.

The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.

Provided is a multiplier-accumulator (MAC) system, circuit, and method. The MAC system includes a MAC circuit, including a plurality of resistors, having respective resistances, a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge, and a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value, wherein the digital value is an accumulation result of the MAC circuit.

A compute-in-memory (CIM) array module and a method for performing dynamic saturation detection for a CIM array are provided. The CIM array module includes a CIM array, saturation detection units (SDUs) and a controller. The CIM array includes selectable row signal lines, column signal lines and cells. Each cell is located at an intersection of a selectable row signal line and a column signal line, and each cell has a programmable conductance. The SDUs are selectively coupled to at least one column signal line, and each SDU is configured to, for each column signal line, generate an analog signal, and identify the column signal line as a saturated column signal line when a voltage of the analog signal is greater than a saturation threshold voltage, or a current of the analog signal is greater than a saturation threshold current.

A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

An array circuit includes a plurality of vector-matrix multiplication (VMM) elements arranged in rows and columns. The VMM elements are configured to collectively perform multiplication of an input vector by a programmed input matrix to generate a plurality of output values that are representative of a result matrix that is the result of multiplication of the input vector and the input matrix. The VMM elements store states of the input matrix. Input voltages to the array are representative of elements of the input vector. A VMM element draws charge from a column read line based upon charging of a capacitor in the VMM. An integrator circuit connected to the column read line outputs a voltage that is indicative of a total charge drawn from the column read line by elements connected to the read line, which voltage is further indicative of an element of a result matrix.

A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.