A method for programming a memory block of a non-volatile memory structure, wherein the method comprises, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.

Apparatuses and techniques are described for detecting latent defects in a memory device by considering both physical segment and logical segment fail bits in an erase operation. The erase operation involves performing a series of erase loops until the memory cells pass an erase-verify test. The passing of the erase-verify test is based on counting memory cells in different logical segments which fail the verify test and determining that the count is less than a logical segment threshold for each logical segment. Subsequently, the technique involves counting memory cells in each physical segment which fail the erase-verify test and determining whether the count is less than a physical segment threshold. If the count is equal to or greater than the physical segment threshold for one or more of the physical segments, the block of memory cells is marked as being bad.

Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can casuse a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

There is provided a method for operating a memory device for performing a program operation of programming data in selected memory cells among a plurality of memory cells. The method includes: applying a program voltage to the selected memory cells; verifying program states of memory cells programmed to any one program state among a plurality of program states distinguished based on a plurality of threshold voltages among the selected memory cells; and verifying an erase state of memory cells programmed to an erase state among the selected memory cells.

A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.

A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Apparatuses and techniques are described for detecting latent defects in a memory device by considering both physical segment and logical segment fail bits in an erase operation. The erase operation involves performing a series of erase loops until the memory cells pass an erase-verify test. The passing of the erase-verify test is based on counting memory cells in different logical segments which fail the verify test and determining that the count is less than a logical segment threshold for each logical segment. Subsequently, the technique involves counting memory cells in each physical segment which fail the erase-verify test and determining whether the count is less than a physical segment threshold. If the count is equal to or greater than the physical segment threshold for one or more of the physical segments, the block of memory cells is marked as being bad.