According to one embodiment, a semiconductor storage device includes strings each with a first select transistor, memory cell transistors, and a second select transistor connected in series. Word lines are provided, each connected to memory cell transistors in a same position across the strings. A bit line is connected in common to a first end of each of the strings. A source line is connected in common to a second end of each of the strings. A control circuit is configured to perform an erase operation on strings. The control circuit adjusts, for each of the strings, either an application time of a first voltage applied to a gate of the first select transistor of the respective string in the erase operation or a voltage level of the first voltage applied to the gate of the first select transistor of the respective string in the erase operation.

A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed.

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

A three dimension memory device, such as a three dimensional AND flash memory is provided. The three dimension memory device includes a plurality of memory arrays, a plurality of bit line switches, and a plurality of source line switches. The memory array has a plurality of memory cell rows respectively coupled to a plurality of source lines and bit lines. The bit line switches and the source line switches are respectively implemented by a plurality of first transistors and second transistors. The first transistors are coupled to a common bit line and the bit line. The second transistors are coupled to a common source line and the source lines. The first transistors are P-type transistors or an N-type transistors with a triple-well substrate, and the second transistors are P-type transistor or an N-type transistors with a triple-well substrate.

A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a secondary predetermined voltage being lower than the primary predetermined voltage to a secondary location of the memory apparatus and measuring a leak current at the primary location. The control means then determines the erase operation passed in response to the leak current measured not being greater than a predetermined leak threshold.

In a method of reducing reliability degradation of a nonvolatile memory device, the nonvolatile memory device in which initial data having an initial threshold voltage distribution is stored in a plurality of memory cells connected to a plurality of wordlines is provided. Before a first process causing reliability degradation is performed, a first write operation is performed such that first data having a first threshold voltage distribution is stored into memory cells connected to first wordlines. The first wordlines have a degree of reliability degradation less than a reference value. Before the first process is performed, a second write operation is performed such that second data having a second threshold voltage distribution is stored into memory cells connected to second wordlines. The second wordlines have a degree of reliability degradation greater than or equal to the reference value.

Technology is disclosed for applying a positive temperature coefficient (Tco) voltage to a control terminal of a dummy select transistor. The dummy select transistor resides on a NAND string having non-volatile memory cells and a regular select transistor. The dummy select transistor is typically ON (or conductive) during memory operations such as selected string program, read, and verify. In an aspect, the positive Tco voltage is applied to the control terminal of a dummy select transistor during a program operation. Applying the positive Tco voltage during program operations reduces or eliminates program disturb to the dummy select transistor. In some aspects, the dummy select transistor is used to generate a gate induced drain leakage (GIDL) current during an erase operation. In some aspects, the dummy select transistor is a depletion mode transistor.

A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.

Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.