As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.

The present invention relates to resistive random access memory (ReRAM). Disclosed are a ReRAM and write operation method thereof. The write operation method comprises monitoring, under a pre-operation signal bias, whether a conversion from a high resistance stage (HRS)/low resistance stage (LRS) to a LRS/HRS begins to occur, and controlling a change in a conversion operation signal, thus conducting a setting/resetting operation. The write operation method improves the storage performance of the ReRAM.

A read-write circuit mainly includes a read circuit and a write circuit. The write circuit comprises: a first voltage selector and a first voltage follower circuit that is electrically connected to the memristor storage array. The read-write circuit further includes a second voltage selector and a second voltage follower circuit that is electrically connected to the memristor storage array. Voltage stable following during bipolar writing is selected through the foregoing selector. Meanwhile, the reading circuit is provided with a variable resistor to select an access mode. The actual read-out voltage and the output voltage passing through the reference resistor under the same read voltage are input into a differential amplifier to obtain read-out data.

The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.

Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same.

An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

A memory device, and a method of making the same, includes a resistive random-access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor consisting of an epitaxially grown material that forms the bottom electrode of the resistive random-access memory element. Additionally, a method of writing to the memory device includes applying a first voltage on a word line of the memory device to form a filament in the resistive random-access memory element. A second voltage including an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element.