Provided is a semiconductor device including a substrate, a tunneling insulating film disposed on the substrate, a control gate electrode disposed on the tunneling insulating film, a first floating gate electrode disposed between the control gate electrode and the tunneling insulating film, a second floating gate electrode disposed between the first floating gate electrode and the tunneling insulating film, a first control gate insulating film disposed between the first floating gate electrode and the control gate electrode, a second control gate insulating film disposed between the second floating gate electrode and the first floating gate electrode, and a source electrode and a drain electrode disposed on the substrate to be spaced apart from each other with respect to the control gate electrode, wherein the control gate electrode includes a first metal material, wherein the first floating gate electrode includes a second metal material, wherein the second floating gate electrode includes a third metal material, wherein the first to third metal materials are different from each other, wherein an oxidizing power of the second metal material is smaller than an oxidizing power of the first metal material.

A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.

A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.

A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.

A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.

A memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

Disclosed herein are related to a memory device including a memory cell and a bias supply circuit providing a bias voltage to the memory cell. In one aspect, the bias supply circuit includes a bias memory cell coupled to the memory cell, where the bias memory cell and the memory cell may be of a same semiconductor conductivity type. The memory cell may include at least two gate electrodes, and the bias memory cell may include at least two gate electrodes. In one configuration, the bias memory cell includes a drain electrode coupled to one of the at least two gate electrodes of the bias memory cell. In this configuration, the bias voltage provided to the memory cell can be controlled by regulating or controlling current provided to the drain electrode of the bias memory cell.

For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.