A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.

A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells of the strings in particular ones of the rows and associated with the at least one edge word line to have an altered distribution of the threshold voltage for one or more of the data states compared to the memory cells of the strings not in particular ones of the rows and not associated with the at least one edge word line during a program operation.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a secondary predetermined voltage being lower than the primary predetermined voltage to a secondary location of the memory apparatus and measuring a leak current at the primary location. The control means then determines the erase operation passed in response to the leak current measured not being greater than a predetermined leak threshold.

A multi time program device with a power switch and a non-volatile memory implementing the power switch for multi time program is provided. The device performs a program operation or an erase operation of a non-volatile memory cell in a non-volatile memory device.

Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

A semiconductor memory device may include a second conductive type first well, a second conductive type third well, a first conductive type second well, a floating gate and a selection gate. The first well may include a first active region. The third well may include a third active region. The second well may be arranged between the first well and the third well. The second well may include a second active region. The floating gate may be overlapped with the first active region, the second active region and the third active region. The selection gate may be overlapped with the second active region. The selection gate and the floating gate may be arranged side by side. A second overlap area between the second active region and the floating gate may be larger than a third overlap area between the third active region and the floating gate.

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.

A memory system includes: a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines; and a controller configured to control the nonvolatile memory device to perform a read operation on the plurality of memory blocks, wherein the read operation includes: a first operation of supplying a first voltage level to the plurality of word lines, a second operation of discharging the plurality of word lines to a second voltage level, a third operation of supplying a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation of discharging the plurality of word lines to a fourth voltage level.