In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.

A storage apparatus includes a non-volatile memory and a controller to determine whether or not to compress data at a time when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. The update frequency level may indicate whether data is Hot or Cold. On the basis of the update frequency level of the specified logical address range, the device controller determines whether to compress the specified data. When a determination is made to compress the specified data, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory which may be a flash memory device. A degradation rank of physical blocks in the flash memory may include at least Young and Old. Reclamation processing including selecting a migration destination on the basis of the updated frequency level may also be performed. When a determination is made not to compress the specified data, the device controller writes the specified data into the non-volatile memory.

Disclosures of the present invention describe a method of performing feedforward and recurrent operations in an artificial neural network using nonvolatile memory cells. In the present invention, a plurality of nonvolatile memory cells or a memory array consists of the nonvolatile memory cells and necessary circuit units are integrated to form an artificial neural network (ANN). Therefore, it is able to perform feedforward and recurrent operations in the MN numbers of nonvolatile memory cells storing with different weights through the self-training learning function of the ANN.

A memory device may include: a memory cell array including a plurality of memory cells; and a control circuit suitable for programming the memory cell array. The control circuit may program the memory cell array according to a predetermined coding method, such that read voltage levels for multi-sensing are minimized and the numbers of read operations for logical pages are distributed. Therefore, the memory device can improve the cell distribution for the plurality of memory cells and the performance of read timing.

A semiconductor device includes a first storage unit including twin cells which are electrically rewritable and complementarily store 1-bit data based on a difference in a threshold voltage, a second storage unit including a memory cell which is electrically rewritable, data stored in the memory cell being erased when data in the twin cells is erased, at least one scrambler subjecting first data to a scramble processing by using scramble data to generate second data, a first write circuit which writes the second data into the twin cells in the first storage unit, a second write circuit which writes the scramble data into the memory cell in the second storage unit, and at least one descrambler subjecting the second data read from the first storage unit to a descramble processing by using the scramble data read from the second storage unit.

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

A semiconductor memory device includes a substrate, a controller, a semiconductor memory component, first and second capacitors, and a jumper element. The substrate has a conductor pattern. The conductor pattern includes a first conductor portion and a second conductor portion. The first conductor portion overlaps at least a part of the first capacitor in a thickness direction of the substrate and is electrically connected to the first capacitor. The second conductor portion overlaps at least a part of the second capacitor in the thickness direction of the substrate and is electrically connected to the second capacitor. The first conductor portion and the second conductor portion are separated from each other, and are electrically connected to each other by the jumper element.

A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.