A semiconductor chip with error detection and correction includes multiple pipes and each pipe is coupled to one or more ports on the semiconductor chip. The semiconductor chip further includes a state machine coupled to the pipes to generate a number of events consisting of read- and/or scan-type events associated with a plurality of storage elements. The state machine is implemented in hardware and can centrally detect and correct erroneous memory entries across the plurality of storage elements.

A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.

A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

A method for testing a memory chip includes the following: test data is written into memory cells of a memory chip to be tested; stored data is read from memory cells; a test result of the memory chip to be tested is generated according to the test data and the stored data. A current voltage of bit line precharge (VBLP) of the memory chip to be tested is smaller than a standard VBLP of the memory chip to be tested, and/or a current sensing delay time (SDT) of the memory chip to be tested is smaller than a standard SDT of the memory chip to be tested.

A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

A receiver includes the following: a signal receiving circuit, including a first MOS transistor and a second MOS transistor, where a gate of the first MOS transistor is configured to receive a reference signal and a gate of the second MOS transistor is configured to receive a data signal, and the signal receiving circuit is configured to output a comparison signal, the comparison signal being configured to represent a magnitude relationship between a voltage value of the reference signal and a voltage value of the data signal; and an adjusting circuit, including a third MOS transistor, where a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to a drain of the first MOS transistor, and a gate of the third MOS transistor is configured to receive an adjusting signal.

A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.