Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.

A storage system includes: a control processor, configured to: read user data with a read threshold, detect a correctable data error in the user data, adjust the read threshold to correct the correctable data error, read a 1 and 0 counter to determine which threshold adjustment range has been activated, generate an adjusted read threshold, based on the threshold adjustment range, to update an optimal read threshold set; and read the user data in a physical block using the adjusted read threshold.

Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

The present embodiments provides a memory repair solution finding device and method which find a fault by testing a memory and find a repair solution in parallel and dynamically reconfigure the stored fault information to minimize a repair solution searching time with an optimal repair rate.

A semiconductor device includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion provides a plurality of memory components, including a first substrate layer, a plurality of first interconnect conductive layers, a plurality of first conductive vias, and a plurality of first conductive contacts. The first conductive contacts electrically connect to the first conductive vias, and the first conductive contacts in combination with the first conductive vias are formed on a top first interconnect conductive layer of the first interconnect conductive layers. The second semiconductor portion provides a control circuit, including a second substrate layer and a plurality of second interconnect conductive layers. The first and second semiconductor portions are stacked vertically with one another, so that the first conductive contacts are electrically connected to the control circuit, and the first conductive contacts in combinations with the first conductive vias form a plurality of transmission channels.

An image processing apparatus including a plurality of transfer units, a data storage, an image processing processor, and a test circuit. A plurality of captured image data are respectively assigned to the plurality of transfer units and the plurality of transfer units transfer the assigned image data. The data storage unit stores the plurality of image data which are transferred by the plurality of transfer units. The image processing processor performs image processing on the plurality of image data which are stored in the data storage unit. The test circuit tests the image processing processor in a period during which the image data are not input from the data storage unit to the image processing processor.

The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

According to one embodiment, an arithmetic device includes a first computational circuit including a first string, the first string having a first magnetoresistive effect element on a first conducting layer; a second computational circuit including a second strings, the second string having second magnetoresistive effect element on a second conducting layer; a third computational circuit executing computational processing using a first signal from the first computational circuit and a second signal from the second computational circuit; and a control circuit. The control circuit sets a condition on write operations with respect to at least one of the first and second magnetoresistive effect elements, based on information related to write error in at least one of the first and second magnetoresistive effect elements.

An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.