A test socket for an IC chip includes a retainer positioned adjacent a load board, the retainer defining a plurality of apertures corresponding to contact pads on the load board; a plurality of contacts disposed in the plurality of apertures, the plurality of contacts configured to electrically couple the IC chip to the contact pads; a housing defining a chamber in fluid communication with an inlet, a liquid outlet, and a vapor outlet. The housing includes a body structure defining a plurality of cavities corresponding to the plurality of apertures and configured to receive the plurality of contacts therein, and a guide structure configured to receive the IC chip and position the IC chip in the chamber when engaged with the plurality of contacts. The chamber receives a two phase fluid coolant via the inlet to at least partially submerges the plurality of contacts in the two phase fluid coolant.

A test socket includes: a first body including a fixing portion configured to receive a sample having a plurality of test terminals; a second body facing the first body and coupled with the first body such that the second body rotates relative to the first body about a hinge pin; a test board provided on the second body and configured to test the sample, wherein the test board has a plurality of first openings provided therein; and a plurality of interface pins penetrating through the first openings, wherein each of the plurality of interface pins includes a contact pin and a spring, wherein the contact pin is provided in a first end portion of each of the plurality of interface pin and is configured to come into contact with a test terminal of the plurality of test terminals, and the spring elastically supports the contact pin.

A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.

A test apparatus and an automatic test equipment having the same are disclosed. The test apparatus includes a test head having a test area, a socket board combined to the test area of the test, the socket board including a socket body and an active device attached on a first surface of the socket body, the active device configured to operate a semiconductor package, and a heat exchanger arranged on an upper portion of the test head, the heat exchanger being in contact with the socket board.

A wafer test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.

Examples described herein provide a wearout card and a method for using the wearout card. The wearout card generally includes a first set of connectors configured to connect the testing apparatus to a testing controller, and a second set of connectors configured to connect the testing apparatus to a device under test (DUT). The wearout card can also include a memory configured to store identifying information of the testing apparatus and a use counter indicating a number of times different DUTs have been connected to the second set of connectors.

A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

A stand-alone active thermal interposer device for use in testing a system-in-package device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

A probe card includes a sub-board, having a heating layer, connected to a probe pin. A main board is connected to the sub-board and includes a first output terminal configured to output first power received from a first power supply to the heating layer in a first mode. A power converter is configured to lower a first voltage corresponding to residual power received from the first power supply to a second voltage and output the residual power in a second mode. A second output terminal is configured to receive the residual power from the power converter and second power from a second power supply and output third power including the residual power and the second power to a device under test in the second mode. A first switch unit is connected to the first power supply, the first output terminal, and the power converter.

A burn-in board includes: a board; sockets mounted on the board; a connector mounted on the board; and wiring systems disposed in the board and connecting the sockets and the connector. The wiring systems comprise: a first wiring system that transmits a first signal; and a second wiring system that transmits a second signal different from the first signal, and a type of a first connection form of the first wiring system is different from a type of a second connection form of the second wiring system.