An electronic unit comprises a microcontroller with a control input, a control output, and a signal input; and an interface circuit with a connection terminal, a control output, a control input, and a signal output. Both the microcontroller and the interface circuit each have a first operating mode and a second operating mode. The microcontroller is designed to cause the interface circuit to operate in its first operating mode. The interface circuit is designed to convert an input signal into a derivation signal representing a derivation of the input signal over time and to generate a control signal from the derivation signal. The microcontroller is designed to cause the interface circuit to operate in its second operating mode and to receive and convert a digital input signal and to output an output signal to the microcontroller.

A processing unit is configured differently based on an identified workload, and each configuration of the processing unit is exposed to software (e.g., to a device driver) as a different virtual processing unit. Using these techniques, a processing system is able to provide different configurations of the processing unit to support different types of workloads, thereby conserving system resources. Further, by exposing the different configurations as different virtual processing units, the processing system is able to use existing device drivers or other system infrastructure to implement the different processing unit configurations.

A point-of-sale (POS) device includes a processor, a battery, a transaction object reader, a printer with a printer controller, and optionally a temperature sensor. The processor determines a present power discharge capability rate of the battery, optionally based on a temperature measured by the temperature sensor. The processor also calculates a first estimated power draw rate based on a first setting value for at least one of the components of the POS device, such as the printer. If the first estimated power draw rate is dangerously close to the present power discharge capability rate of the battery, a second estimated power draw rate is calculated based on a second setting value for the one or more components. If the second estimated power draw rate is no longer dangerously close to the present power discharge capability rate of the battery, the components are set to the second settings value.

Examples described herein provide for a first core to map a measurement of packet processing activity and operating parameters so that a second core can access the measurement of packet processing activity and potentially modify an operating parameter of the first core. The second core can modify operating parameters of the first core based on the measurement of packet processing activity. The first and second cores can be provisioned on start-up with a common key. The first and second cores can use the common key to encrypt or decrypt measurement of packet processing activity and operating parameters that are shared between the first and second cores. Accordingly, operating parameters of the first core can be modified by a different core while providing for secure modification of operating parameters.

Systems and methods are disclosed for processor power management using instruction throttling. For example, an integrated circuit may include a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

An apparatus can include processor cores and control circuitry coupled to the processor cores. The control circuitry can detect at least one of a power characteristic and a frequency characteristic of at least one of the processor cores. The control circuitry can determine that a frequency control opportunity is present on at least one of the processor cores based on at least one of the power characteristic and the frequency characteristic. The control circuitry can adjust a power parameter of at least one of the processor cores responsive to determining that the frequency control opportunity is present.

Described are systems and methods for power management. A processing system includes one or more cores and a connected power management unit (PMU). The PMU is selected from one of: a first level PMU which can power scale a; a second level PMU which can independently control power from a shared cluster power supply to each core of two or more cores in a cluster; a third level PMU where each core includes a power monitor which can track power performance metrics of an associated core; and a fourth level PMU when a complex includes multiple clusters and each cluster includes a set of the one or more cores, the fourth level PMU including a complex PMU and a cluster PMU for each of the multiple clusters, the complex PMU and cluster PMUs provide two-tier power management. Higher level PMUs include power management functionality of lower level PMUs.

A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

Examples are disclosed that relate to allocating power to peripheral device interfaces. One example provides, at a computing device, a method, comprising obtaining a measurement of power consumption by one or more peripheral devices, and based at least on the measurement and on a maximum power tolerance of a power source, allocating to each respective interface a minimum portion of power output from the power source. The method further comprises rendering a remainder of the maximum power tolerance available for consumption by one or more processors, the remainder including the maximum power tolerance minus a sum of the minimum portions, where the remainder and a system portion of power output are available for consumption by the one or more processors, and where a performance attribute of the one or more processors is not throttled while total power consumption does not exceed a threshold power output from the power source.