A storage system includes a storage device and a host device. The storage device includes a nonvolatile memory device having a first size and a first volatile memory device having a second size smaller than the first size and configured to operate as a cache memory with respect to the nonvolatile memory device. The first volatile memory device is configured to allow a first bus portion access to cache data stored in the first volatile memory device. The host device is configured to generate a cache table corresponding to information in the cache data stored in the first volatile memory device and configured to read the cache data stored in the first volatile memory device via the first bus portion based on the cache table.

As the volume of data under management expands rapidly, so do the costs associated with storing and that data on secondary storage devices. The illustrative approach provides an improvement to the information management system by delaying certain tasks that meet a set of criteria until a specified threshold is met. The system receives a request to be performed on a set of data stored on secondary devices. Power management module determines whether the task satisfies a set of criteria for delayed execution, queues the task, and when a specified threshold of the queued tasks is met powers up the necessary components to execute the tasks.

The present disclosure generally relates to optimizing device interrupt coalescing based upon host device behavior. The data storage device maintains three functional states: a training state, a holding state, and a retraining state. The data storage device switches between states based upon host device behavior as well as the behavior of the data storage device. Once the data storage device finds the optimum conditions for coalescing, the data storage device will periodically test the conditions to adapt to changing host device behavior as well as data storage device behavior. In so doing, the data storage device can dynamically adjust interrupt coalescing to ensure optimum operation of the storage device.

A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

A method described herein involves identifying a first time associated with a read operation that retrieves data of a write unit at a memory sub-system, identifying a second time associated with a write operation that stored the data of the write unit at the memory sub-system, and performing a refresh operation for the data of the write unit at the memory sub-system based on a difference between the first time associated with the read operation and the second time associated with the write operation.

Techniques manage a redundant array of independent disks. In such a technique, a response time of a first storage device in the RAID is compared to a first threshold. In response to the response time of the first storage device exceeding the first threshold, the first storage device is configured as a pseudo-degraded storage device, such that the pseudo-degraded storage device is responsive to write requests only.

The described technology is generally directed towards an input/output (I/O) load balancer of a data storage system that detects an I/O overloaded (“hot”) storage unit and logically moves its hot data to a non-overloaded (“cold”) storage unit. Threshold load levels can be used to determine hot and cold storage units. In one implementation, new writes to the hot storage unit are prevented while its hot data is logically moved to a cold storage unit. To avoid reads from the hot storage unit, the hot data can be recreated from redundant data obtained via a recovery path. To avoid a capacity imbalance, once enough hot data has been moved so that the (formerly) hot storage device is no longer considered hot, cold data from the cold storage device can be written to the formerly hot storage device. New data writes to the formerly hot storage device can then resume.

Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.

The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.