A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The module controller is configurable to control data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller includes a data selection circuit configurable to pre-search data transferred from the non-volatile memory with respect to one or more search criteria before providing the pre-select data relevant to the one or more search criteria to the volatile memory subsystem.

An electronics assembly including a plurality of midplanes positioned between and coupled to a plurality of electronic components at one side of the plurality of midplanes and at least one electronic component at an opposite side of the plurality of midplanes in a manner so that the midplanes are vertically oriented in parallel relative to each other so as to define spaces therebetween. The midplanes each include electrical traces configured to send signals among and between the plurality of electronic components at the one side of the midplanes and the at least one electronic component at the opposite side of the midplanes.

A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Switch topology-aware path selection in an information processing system is provided. For example, an apparatus comprises a host device comprising a processor coupled to a memory. The host device is configured to communicate with a storage system over a network with a plurality of switches. The host device is further configured to obtain topology information associated with the plurality of switches in the network, and select a path from the host device to the storage system through one or more of the plurality of switches based at least in part on the obtained topology information.

A memory system includes a plurality of memory groups capable of performing a data input/output operation, and a controller configured to divide an operation subject to a data input/output command into at least one unit operation corresponding to the plurality of memory groups, and assign the at least one unit operation to plural queues corresponding to the respective memory groups, based on first information regarding operation statuses of the plurality of memory groups and second information regarding available resources.

Methods, systems, and devices supporting switchable lane directions between a host system and a memory system are described. A host system may communicate with a memory system using a set of lanes, where each lane may send information (e.g., commands, operations, data) in a specific direction. In some cases, the host system and memory system may support one or more switchable lanes, where both systems include transmit and receive modules for the lane. According to a bandwidth condition associated with a specific direction satisfying a threshold for reconfiguring a lane, the host system and the memory system may switch a direction configured for a lane. Switching the lane direction may increase the supported bandwidth in a specific direction, for example, from the host system to the memory system (e.g., in a “write optimized” configuration) or from the memory system to the host system (e.g., in a “read optimized” configuration).

Improving performance of garbage collection (GC) processes in a deduplicated file system having a layered processing architecture that maintains a log structured file system storing data and metadata in an append-only log arranged as a monotonically increasing log data structure of a plurality of data blocks wherein a head of the log increases in chronological order and no allocated data block is overwritten. The storage layer reserves a set of data block IDs within the log specifically for the garbage collection process, and assigns data blocks from the reserved set to GC I/O processes requiring acknowledgment in a possible out-of-order manner relative to an order of data blocks in the log. It strictly imposes using in-order I/O acknowledgement for other non-GC processes using the storage layer, where these processes may be deduplication backup processes using a segment store layer at the same protocol level as the GC layer.

A technique for handling memory access requests is described. An apparatus has an interconnect for coupling a plurality of requester elements with a plurality of slave elements. The requester elements are arranged to issue memory access requests for processing by the slave elements. An intermediate element within the interconnect acts as a point of serialisation to order the memory access requests issued by requester elements via the intermediate element. The intermediate element has tracking circuitry for tracking handling of the memory access requests accepted by the intermediate element. Further, request acceptance management circuitry is provided to identify a target slave element amongst the plurality of slave elements for that given memory access request, and to determine whether the given memory access request is to be accepted by the intermediate element dependent on an indication of bandwidth capability for the target slave element.

Disclosed are various embodiments for improving the resiliency and performance of cluster memory. First, a computing device can submit a write request to a byte-addressable chunk of memory stored by a memory host, wherein the byte-addressable chunk of memory is read-only. Then, the computing device can determine that a page-fault occurred in response to the write request. Next, the computing device can copy a page associated with the write request from the byte-addressable chunk of memory to the memory of the computing device. Subsequently, the computing device can free the page from the memory host. Then, the computing device can update a page table entry for the page to refer to a location of the page in the memory of the computing device.

A system and method for updating a configuration of a host system so that the memory sub-system of the host system emulates performance characteristics of a target memory sub-system. An example system determining a configuration of the host system, the host system comprising a memory sub-system; receiving, by a processing device, a request to emulate a characteristic of a target memory sub-system; analyzing a plurality of candidate configurations for the host system, wherein the plurality of candidate configurations comprises a candidate configuration that generates a load on the memory sub-system to decrease characteristics of the memory sub-system; and updating the configuration of the host system based on the plurality of candidate configurations, wherein the updated configuration changes the memory sub-system to emulate the characteristic of the target memory sub-system.