A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.

A system includes a memory device storing groups of managed units and a processing device operatively coupled to the memory device. The processing device is to, during power on of the memory device, perform including: causing a read operation to be performed at a subset of a group of managed units; determining a bit error rate related to data read from the subset of the group of managed units; and in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.

A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.

A processing device in a memory system identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field. The processing device identifies a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field. The processing device determines that a value representing a page number stored in the page field satisfies a threshold criterion. Responsive to determining that the value representing the page number satisfies the threshold criterion, the processing device determines a difference between the value representing the page number and a threshold value associated with the threshold criterion plurality of block stripes on a memory device. The processing device stores a value representing the difference as a plurality of bits of the second set of bits. The processing device stores a value representing a block number stored in the block field as a plurality of bits of the first set of bits.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.

Exemplary methods, apparatuses, and systems include receiving a plurality of read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets. The size of the current set is a first number of read operations. An aggressor read operation is selected from the current set. A first data integrity scan is performed on a victim of the aggressor and a first indicator of data integrity is determined based on the first data integrity scan. A scaling factor is determined using the indicator of data integrity and a number of program erase cycles for the portion of memory. The set size of read operations is adjusted to a second number of read operations using the scaling factor for a subsequent set.

A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.

A degree of fragmentation is determined based on a number of holes present in a storage system layout or a portion of a layout. Edges between the holes and used portions of the storage system are tabulated by scanning a storage space. The occurrences of a pattern of used/available allocation units and/or the occurrences of another pattern available/used allocation units are recognized. A fragmentation value is calculated based on occurrences of the patterns in view of the total storage space. The present fragmentation measurement system utilizes the number of occurrences of the holes in assessing fragmentation.

Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.