A method for the secured storing of a data element in an external memory, which is connected to a microcontroller via an interface module, which is configured to calculate memory addresses for data to be stored and for error correction values. The method includes receiving the data element to be stored by the interface module, a calculation by the interface module of a memory address in the external memory for the data element to be stored, and a writing, starting at the memory address, of the data element and of the error correction value via the interface module into the external memory, the error correction value immediately following the data element being written and the writing taking place within one addressing phase. A corresponding interface module, a corresponding microcontroller, and a corresponding control unit are also described.

Described is a system for detecting corruption in a deduplicated object storage system accessible by one or more microservices while minimizing costly read operations on objects. A similarity group verification path is selected based upon detection of an object storage memory size condition. The similarity group verification path is performed by one or more worker nodes. The similarity group verification path includes worker node phases that verify whether objects have been corrupted without having to incur costly read operations.

Event records from multiple computing devices are received at a managing unit. Individual event records include an event identifier field including an event identifier identifying a first event associated with a particular computing device, a parent event identifier field identifying a parent event that initialized the first event, and an entity identifier field including an entity identifier identifying the particular computing device. The managing unit generates log records associated with event identifiers included in the event records. The log records include state fields indicating a state of a particular event associated with a particular event identifier. Based on a correlation of the event and log records, the managing unit determines at least two computing devices associated with events resulting in an error state, and identifies parent events that initialized the events with errors. The managing unit generates a report linking the parent events to the events having an error state.

An illustrative data storage management system enables a Tenant to retain control over criteria for protecting the Tenant's data, and hides details of the Service Provider's infrastructure. The Service Provider may have many data centers, each one represented within the system by a Resource Pool with attributes that reflect the infrastructure resources of the corresponding data center. A system analysis, which is triggered by the Tenant's choices for data protection, keys in on a suitable Resource Pool. The system analysis identifies suitable system resources within the Resource Pool and associates them to the data source. Subsequent data protection jobs invoke proper system components based on the associations created by the system analysis. In some embodiments, the system will invoke infrastructure resources created on demand when a data protection job is initiated rather than being pre-existing resources.

One embodiment provides a computer implemented method of estimating replication completion time. The method includes creating a historical dataset of prior replication data; determining a set of replication parameters to consider; inputting the historical dataset and the set of replication parameters to a replication completion time estimator module; generating a replication completion time prediction based on the historical dataset and the set of replication parameters; and generating a confidence prediction corresponding to the replication completion time prediction.

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Embodiments relate to the field of storage technologies. The method is applied to a flash device whose first physical storage space stores a data block at a first security level and a data block at a second security level and whose second physical storage space stores a data block at a second security level. The method includes: receiving a data write request used to request to write target data, and obtaining a security level of the target data; and writing the target data into the first physical storage space if the security level of the target data is the first security level; or writing the target data into the second physical storage space or writing the target data into the second physical storage space and the first physical storage space if the security level of the target data is the second security level.

Systems and methods for replacing and testing a data storage device are disclosed. In disclosed embodiments, a system including a data storage array (DSA) including a plurality of data storage devices (DSDs) in an enclosure. The system further includes an I/O server coupling the DSA to a client node and configured to provide data access between the client node and the DSA. The system further includes a management server coupled to the DSA, configured to detect a failed DSD in the DSA, detect a replacement DSD in the enclosure that replaces the failed DSD, and add the replacement DSD to a logical path of the DSA. The management server is further configured to display an indication of a state of the DSA based on the comparing.

A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Multiple data paths may be available to a data management system for transferring data between a primary storage device and a secondary storage device. The data management system may be able to gain operational advantages by performing load balancing across the multiple data paths. The system may use application layer characteristics of the data for transferring from a primary storage to a backup storage during data backup operation, and correspondingly from a secondary or backup storage system to a primary storage system during restoration.