A method of operating a non-volatile memory device is provided. The device includes a latch, a page buffer and blocks, each of which includes pages. The method includes: receiving a page command for a write operation corresponding to a page of one of the blocks; receiving a write command for writing data to the page buffer; latching preexisting latched data or random data generated as latched data; writing the latched data to a page of a new block from among the plurality of blocks that corresponds to a page address based on the write command; and repeatedly updating the page address and repeatedly writing the latched data to additional pages corresponding to each updated page address until each page of the new block has been written to.

A memory system is configured to be connected to a host. The memory system includes a non-volatile first memory, a second memory, and a controller configured to manage cache data stored in the second memory in units of a segment such that each segment includes a plurality of pieces of the cache data. Each of the plurality of pieces of the cache data includes mapping information which correlates a logical address value indicating a location in a logical address space provided by the memory system to the host with a location in the first memory. At least two pieces of the cache data are arranged in one segment without a space therebetween.

A processing device in a memory system identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field. The processing device identifies a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field. The processing device determines that a value representing a page number stored in the page field satisfies a threshold criterion. Responsive to determining that the value representing the page number satisfies the threshold criterion, the processing device determines a difference between the value representing the page number and a threshold value associated with the threshold criterion plurality of block stripes on a memory device. The processing device stores a value representing the difference as a plurality of bits of the second set of bits. The processing device stores a value representing a block number stored in the block field as a plurality of bits of the first set of bits.

Examples described herein relate to a network interface device comprising an interface to memory and circuitry. In some examples, the circuitry is to: determine a number of data units stored in a page in the memory and based on no data unit stored in a page of memory, permit storage of a data unit in the page in the memory.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.

Embodiments of the present disclosure provide a system for testing multicore firmware (FW) in a memory system and a method thereof. A test system includes a test device and a storage device including a plurality of flash translation layer (FTL) cores, each FTL core associated with multiple memory blocks. The test device generates test preconditions for the plurality of FTL cores and provides the test preconditions to the plurality of FTL cores, the test preconditions being different from each other. Each of the plurality of FTL cores performs one or more test operations based on a corresponding test precondition of the test preconditions.

A method and system for initiating a garbage collection request. Historical data representative of a level of initiated I/O requests is acquired. A first operational state and a second operational state are determined based on the historical data. The first operational state and second operational state are expressed in an indication of the level of initiated I/O requests to be processed. A number of currently initiated I/O requests is acquired. A determination is made as to whether the number of currently initiated I/O requests is indicative of the first operational state or the second operational state. If the computer system is in the first operational state, the garbage collection request is initiated.

A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.

A degree of fragmentation is determined based on a number of holes present in a storage system layout or a portion of a layout. Edges between the holes and used portions of the storage system are tabulated by scanning a storage space. The occurrences of a pattern of used/available allocation units and/or the occurrences of another pattern available/used allocation units are recognized. A fragmentation value is calculated based on occurrences of the patterns in view of the total storage space. The present fragmentation measurement system utilizes the number of occurrences of the holes in assessing fragmentation.

Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.