A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

In response to receiving a read request for target data, an external address of the target data is obtained from the read request, which is an address unmapped to a storage system; hit information of the target data in cache of the storage system is determined based on the external address; and based on the hit information, an address from the external address and an internal address for providing the target data is determined. The internal address is determined based on the external address and a mapping relationship. Therefore, it can shorten the data access path, accelerate the responding speed for the data access request, and allow the cache to prefetch the data more efficiently.

A method, non-transitory computer readable medium, and device that assists with reducing memory fragmentation in solid state devices includes identifying an allocation area within an address range to write data from a cache. Next, the identified allocation area is determined for including previously stored data. The previously stored data is read from the identified allocation area when it is determined that the identified allocation area comprises previously stored data. Next, both the write data from the cache and the read previously stored data are written back into the identified allocation area sequentially through the address range.

A data processing method is applied to a computing device serving as a blockchain node. The method comprises: acquiring a data processing request; according to the data processing request, determining a current version identifier; according to the data processing request, determining a target key value pair used for processing data, and processing data in the value range of the target value pair; writing a newly produced target value pair into a storage space, wherein the key domain of a key value pair in the storage area stores a key identifier and a version identifier, and the version identifier in the key domain of the newly produced target key value pair is the current version identifier.

A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

A method for execution in a storage network, the method begins by determining a user device group content preference, wherein the user group content includes target content for a user device group and the determining includes predicting future target content for the user group. The method continues by selecting a plurality of network edge units for staging encoded data slices, identifying target content for partial download to the plurality of network edge units and dispersed error encoding the target content to generate a set of encoded data slices. The method then continues by identifying encoded data slices from the set of encoded data slices corresponding to the target content for partial download and determining a partial downloading schedule for sending the encoded data slices for partial download to each network edge unit of the plurality of network edge units. The method continues by facilitating partial downloading of the target content by sending the encoded data slices for partial download to each network edge unit of the plurality of network edge units.

A network device includes: a set of content memory banks including a first memory bank; a parity memory bank; a first memory interface; and a second memory interface. The first memory interface is configured to perform a write operation to write new content data to a location in a first content memory bank in a plurality of partial write operations that are spread over two or more clock cycles, including: generating new parity information for the new content data using old content data at the location in the first content memory bank, and storing the new parity information to the parity memory bank. The second memory interface is configured to perform a read operation at the location in the first content memory bank concurrently while the first memory interface is performing at least one of the plurality of partial write operations.

A storage system manages correspondence relationships between physical addresses and logical addresses inside a storage device, as well as logical spaces provided by a plurality of storage devices, and when a determination is made as to whether first data and second data are stored in the same storage device in a case in which the first data and the second data are exchanged inside a logical space, and the determination is found to be affirmative, the storage device replaces the logical address corresponding to the first data with the logical address corresponding to the second data without changing the physical address of the physical area in which the first data is stored and the physical address of the physical area in which the second data is stored.

A method of operating a nonvolatile memory system including a memory device having a plurality of memory blocks includes selecting a source block among the plurality of memory blocks in the nonvolatile memory system, and performing a reclaim operation for the source block based on the number of program and erase cycles which have been performed on the source block.