A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.

Methods and devices are provided in which a controller of a storage device receives a read command including at least a file pointer of a file, from an application at a host device. The controller retrieves a physical block address (PBA) list associated with file data from a table maintained at the controller using the file pointer. The controller reads data from a memory using the PBA list, and provides the file data to the application at the host device.

A method for managing a memory buffer, a memory control circuit unit, and a memory storage apparatus are provided. The method includes the following steps. Multiple consecutive first commands are received from a host system. A command ratio of read command among the first commands is calculated. The memory storage apparatus is being configured in a first mode or a second mode according to the command ratio and a ratio threshold. A first buffer is configured in a buffer memory to temporarily store a logical-to-physical address mapping table in response to the memory storage device being configured in the first mode, in which the first buffer has a first capacity. A second buffer is configured in the buffer memory in response to the memory storage device being configured in the second mode, in which the second buffer has a second capacity, which is greater than the first capacity.

A method, an electronic device, and a computer program product for inputting and outputting data is disclosed. The method includes receiving a target I/O request for a storage device from an application, determining that a first offset or a second offset is greater than zero, and generating a plurality of I/O requests based on the target address. The I/O requests include a first I/O request for a first data segment in target data and at least one other I/O request for other data segments in the target data. For the first I/O request, the method includes executing a direct I/O operation on the first data segment by bypassing a cache associated with the storage device.

A method includes determining, in accordance with a first ordering, a plurality of read requests for a memory device. The plurality of read requests are added to a memory device queue for the memory device in accordance with the first ordering. The plurality of read requests in the memory device queue are processed, in accordance with a second ordering that is different from the first ordering, to determine read data for each of the plurality of read requests. The read data for the each of the plurality of read requests is added one of a set of ordered positions, based on the first ordering, of a ring buffer as the each of the plurality of reads requests is processed. The read data of a subset of the plurality of read requests is submitted based on adding the read data to a first ordered position of the set of ordered positions of the ring buffer.

Methods, systems, and devices for initializing memory systems are described. A memory system may transmit, to a host system over a first channel, signaling indicative of a first set of values for a set of parameters associated with communicating information over a second channel between a storage device of the memory system and a memory device of the memory system. The host system may transmit, to the memory system, additional signaling associated with the first set of values for the set of parameters. For instance, the host system may transmit a second set of values for the set of parameters, an acknowledgement to use the first set of values, or a command to perform a training operation on the second channel to identify a second set of values for the set of parameters. The memory system may communicate the information over the second channel based on the additional signaling.

Aspects of the present disclosure relate to data cache management. In embodiments, a storage array's memory is provisioned with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots. Additionally, a logical storage volume (LSV) is established with at least one logical block address (LBA) group. Further, at least one of the LSV's LBA groups is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.

A computational storage device includes a non-volatile memory (NVM) device; and a storage controller configured to control the NVM device. The storage controller includes: a computation processor configured to execute an internal application to generate an internal command; a host interface circuit configured to receive a host command from an external host device, to receive the internal command from the computation processor, and to individually process the received host command and the received internal command; a flash translation layer (FTL) configured to perform an address mapping operation based on a result of the processing of the host interface circuit; and a memory interface circuit configured to control the NVM device based on the address mapping operation of the FTL.

A storage device comprises first and second storage devices mounted on respective first and second PCBs (Printed Circuit Boards) that are separated from each other, the first and second PCBs configured to store different data. The first storage device includes a first storage controller, and a first shock sensor that senses an impact of the first storage device to output a first sensor signal. The second storage device includes a second shock sensor different from the first shock sensor, and senses an impact of the second storage device to output a second sensor signal. The first storage controller outputs a first internal control signal that controls an internal operation of the first storage device based on the first sensor signal. The first storage device and the second storage device transmit data to each other based on the first sensor signal and the second sensor signal.

A system comprises a plurality of computing devices that are communicatively coupled via a network and have a file system distributed among them, and comprises one or more file system request buffers residing on one or more of the plurality of computing devices. File system choking management circuitry that resides on one or more of the plurality of computing devices is operable to separately control: a first rate at which a first type of file system requests (e.g., one of data requests, data read requests, data write requests, metadata requests, metadata read requests, and metadata write requests) are fetched from the one or more buffers , and a second rate at which a second type of file system requests (e.g., another of data requests, data read requests, data write requests, metadata requests, metadata read requests, and metadata write requests) are fetched from the one or more buffers.