A system and method employing a distributed hardware architecture, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations are disclosed. A compute node may be implemented independent of a host compute system to manage and to execute data processing operations. Additionally, an unique algorithm architecture and processing system and method are also disclosed. Different types of nodes may be implemented, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations.

A first storage node is connected to a host by using a first network interface card of the first storage node, and is connected to a second storage node by using a second network interface card. The first storage node receives a data processing request from the host, wherein the data processing request carries a target storage address of to-be-processed data, determines the second storage node based on the target storage address of the to-be-processed data, and sends the data processing request to the second storage node by using the second network interface card, wherein the data processing request instructs the second storage node to process the to-be-processed data.

A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to the embodiments of the present disclosure, when result data obtained by derandomizing data included in a flag area is different from reference data after a random data unit is derandomized based on a seed, it is possible to detect an error occurring in the seed in a process of derandomizing the data and to prevent malfunction of firmware in advance by searching for a target seed and derandomizing the random data unit based on the target seed.

A storage device includes first and second memory devices, and a memory controller. The first memory devices correspond to a main data area. The second memory devices correspond to a reserved area. The memory controller is coupled to the first and second memory devices through first and second channels. A number of first memory devices coupled to the memory controller through the first channel is equal to a number of first memory devices coupled to the memory controller through the second channel, and a number of second memory devices coupled to the memory controller through the first channel is different from a number of second memory devices coupled to the memory controller through the second channel. The memory controller selects a memory device on which a write operation is to be performed, based on a memory state of the first and second memory devices.

A storage system and method for multiprotocol handling are provided. In one embodiment, a computing device is provided comprising a plurality of communication channels configured to communicate with a storage system, wherein a first communication channel has a faster data transfer speed than a second communication channel. The computing device also comprises a processor configured to determine a priority level of a command; send the command with an indication of its priority level to the storage system; in response to the command being a high-priority command, use the first communication channel for transferring data for the command; and in response to the command being a low-priority command, use the second communication channel for transferring data for the command. Other embodiments are provided.

A memory controller for controlling a memory device includes a host interface and a background controller. The host interface communicates with a host through a link, determines whether quality of the link has been degraded by monitoring the quality of the link, and performs a link recovery operation on the link when it is determined that the quality of the link is degraded. The background controller controls the memory device to perform a background operation, while the link recovery operation is being performed.

The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.

Systems and methods described herein synchronize events between various components of storage device during the processing of an exception (i.e., an internal error). The storage device can have a plurality of processors which may each coordinate operations on various domains of storage device processing tasks. An exception occurring in one domain may require input and coordination from other domains within the storage device. Each exception may have a list of predetermined steps needed for completion which are coordinated via a series of sync points placed between exception action clusters which perform a series of specific operations until data or processing from another domain is needed to continue processing. The sync points can be utilized to halt processing in one domain until the other domains are in sync and complete one or more exception action operations. In this way, a streamlined and predictable synchronization between domains may occur during an exception.

A server memory device provides highspeed storage to a computer system. The server memory device has a connector that can make electrical coupling with the computer system. The server memory device includes two memory modules, each with one or more memory chips. Each memory module is coupled and bonded with an interposer. Each interposer is coupled and bonded with the server memory device connector. The connector and interposers provide a high-density interconnect that connects two memory modules to a computer system. The server memory device has a form factor that uses a single unit (1U) of a server rack, doubling the memory capacity provided to the computer system through a single unit (1U) equipment rack.