Various embodiments set forth techniques for free space management in a block store. The techniques include receiving a request to allocate one or more blocks in a block store, accessing a sparse hierarchical data structure to identify an allocator page identifying a region of a backing store having a greatest number of free blocks, and allocating the one or more blocks.

The present application relates to a semiconductor memory training method and related devices, belonging to the technical field of semiconductors. The method comprises: obtaining a stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage; setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage; obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; and using the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold.

A method described herein involves identifying a first time associated with a read operation that retrieves data of a write unit at a memory sub-system, identifying a second time associated with a write operation that stored the data of the write unit at the memory sub-system, and performing a refresh operation for the data of the write unit at the memory sub-system based on a difference between the first time associated with the read operation and the second time associated with the write operation.

A method for operating a memory system including a memory device and a controller which controls the memory device includes identifying a target command among a plurality of commands queued in a host command queue; comparing an estimated power with a power limit; checking an estimated de-queuing time in the case where the estimated power is larger than or equal to the power limit; dequeuing the target command from the host command queue to a memory command queue in the case where the estimated de-queuing time is smaller than a predetermined threshold value; de-queueing the target command from the memory command queue to the memory device; and performing an operation corresponding to the target command.

Portions of configuration state registers in-memory. An instruction is obtained, and a determination is made that the instruction accesses a configuration state register. A portion of the configuration state register is in-memory and another portion of the configuration state register is in-processor. Processing associated with the configuration state register is performed. The performing processing is based on a type of access and whether the portion or the other portion is being accessed.

The described technology is generally directed towards an input/output (I/O) load balancer of a data storage system that detects an I/O overloaded (“hot”) storage unit and logically moves its hot data to a non-overloaded (“cold”) storage unit. Threshold load levels can be used to determine hot and cold storage units. In one implementation, new writes to the hot storage unit are prevented while its hot data is logically moved to a cold storage unit. To avoid reads from the hot storage unit, the hot data can be recreated from redundant data obtained via a recovery path. To avoid a capacity imbalance, once enough hot data has been moved so that the (formerly) hot storage device is no longer considered hot, cold data from the cold storage device can be written to the formerly hot storage device. New data writes to the formerly hot storage device can then resume.

A system and method for logging state data from a power system control device on a computer system is disclosed. The computer system includes a power system supplying power to the computer system. The power system has a power-up sequence having a plurality of stages. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit having states corresponding to the stages of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes the state of the finite state machine circuit in the storage buffer. An external controller is coupled to the communication interface and is operable to read the stored state data.

Disclosed are systems and methods by which a storage device may process and return I/O commands to a host in the order in which the host provided the commands, thereby reducing host overhead, including but not limited to the following: receiving a first I/O command and a second I/O command, the first I/O command and the second I/O command being assigned a sequence tag, issuing the first I/O command and the second I/O command to one or more storage channels based on their respective sequence tags, collecting a command completion notice of the first I/O command or the second I/O command when the first I/O command or the second I/O command has been respectively completed; and issuing a command completion notification to a host based on the sequence tag of the associated completed first I/O command or the second I/O command.

Provided are systems, methods, and apparatuses for managing storage device memory. A method can include receiving, from a host, a command for managing the memory; performing, by the storage device, the command on first data stored on the memory via at least one processing element in the storage device to generate second data; and transmitting, by the storage device, third data based on the second data to the host.

Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.